Update MDE Library instances according to code review comments.

[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / IpfCache.c

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index a46df594973f69b294f42d6641be37cdf1a6c09e..fc6ea25d5202bea65d51dff35dca66091fa5850e 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -1,7 +1,7 @@
 /** @file\r
   Cache Maintenance Functions.\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -12,10 +12,6 @@
 \r
 **/\r
 \r
-\r
-//\r
-// Include common header file for this module.\r
-//\r
 #include <Base.h>\r
 #include <Library/CacheMaintenanceLib.h>\r
 #include <Library/BaseLib.h>\r
@@ -26,9 +22,6 @@
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r
 \r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
 **/\r
 VOID\r
 EFIAPI\r
@@ -36,7 +29,7 @@ InvalidateInstructionCache (
   VOID\r
   )\r
 {\r
-  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES, 0);\r
+  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
 }\r
 \r
 /**\r
@@ -61,7 +54,7 @@ InvalidateInstructionCache (
 \r
   @param  Length  The number of bytes to invalidate from the instruction cache.\r
 \r
-  @return Address of cahce invalidation.\r
+  @return Address of cache invalidation.\r
 \r
 **/\r
 VOID *\r
@@ -71,6 +64,7 @@ InvalidateInstructionCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
   return IpfFlushCacheRange (Address, Length);\r
 }\r
 \r
@@ -90,7 +84,7 @@ WriteBackInvalidateDataCache (
   VOID\r
   )\r
 {\r
-  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES, 0);\r
+  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
 }\r
 \r
 /**\r
@@ -172,7 +166,7 @@ WriteBackDataCache (
                   mode, then Address is a virtual address.\r
   @param  Length  The number of bytes to write back from the data cache.\r
 \r
-  @return Address of cache wrote in main memory.\r
+  @return Address of cache written in main memory.\r
 \r
 **/\r
 VOID *\r
@@ -204,6 +198,10 @@ InvalidateDataCache (
   VOID\r
   )\r
 {\r
+  //\r
+  // Invalidation of entire data cache without writing back is not supported on\r
+  // IPF architecture, so write back and invalidate operation is performed.\r
+  //\r
   WriteBackInvalidateDataCache ();\r
 }\r
 \r
@@ -241,5 +239,10 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+  //\r
+  // Invalidation of a data cache range without writing back is not supported on\r
+  // IPF architecture, so write back and invalidate operation is performed.\r
+  //\r
   return IpfFlushCacheRange (Address, Length);\r
 }\r