Update MDE Library instances according to code review comments.

[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / x86Cache.c

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
index 1fc2b95daa999c25f32b6c038d487f4460fe5d6b..8b169c22444fac664eedc8017e36986d5fe5aa01 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
@@ -1,7 +1,7 @@
 /** @file\r
   Cache Maintenance Functions.\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -13,9 +13,6 @@
 \r
 **/\r
 \r
-//\r
-// Include common header file for this module.\r
-//\r
 #include <Base.h>\r
 #include <Library/BaseLib.h>\r
 #include <Library/DebugLib.h>\r
@@ -30,9 +27,6 @@
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r
 \r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
 **/\r
 VOID\r
 EFIAPI\r
@@ -130,7 +124,8 @@ WriteBackInvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  UINTN                             Start, End;\r
+  UINTN                             Start;\r
+  UINTN                             End;\r
 \r
   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
 \r
@@ -192,7 +187,7 @@ WriteBackDataCache (
                   mode, then Address is a virtual address.\r
   @param  Length  The number of bytes to write back from the data cache.\r
 \r
-  @return Address of cache wrote in main memory.\r
+  @return Address of cache written in main memory.\r
 \r
 **/\r
 VOID *\r
@@ -259,5 +254,9 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
+  //\r
+  // Invalidation of a data cache range without writing back is not supported on\r
+  // x86 architecture, so write back and invalidate operation is performed.\r
+  //\r
   return WriteBackInvalidateDataCacheRange (Address, Length);\r
 }\r