Fix some typo.

[mirror_edk2.git] / MdePkg / Library / BaseLib / BaseLib.inf

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 324bf9d4db000eb62351f3d66ff28c2cb11288cc..3a38f2ba1cac3360a27a857d4a5eb58382718f11 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,8 +1,7 @@
 #/** @file\r
-# Component description file for Base Library\r
-#\r
 # Base Library implementation.\r
-# Copyright (c) 2007, Intel Corporation.\r
+#\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
@@ -21,9 +20,6 @@
   MODULE_TYPE                    = BASE\r
   VERSION_STRING                 = 1.0\r
   LIBRARY_CLASS                  = BaseLib \r
-  EDK_RELEASE_VERSION            = 0x00020000\r
-  EFI_SPECIFICATION_VERSION      = 0x00020000\r
-\r
 \r
 #\r
 #  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
@@ -148,7 +144,7 @@
   Ia32/EnablePaging32.c | MSFT \r
   Ia32/EnableInterrupts.c | MSFT \r
   Ia32/EnableDisableInterrupts.c | MSFT \r
-  Ia32/DivU64x64Remainder.c | MSFT \r
+  Ia32/DivU64x64Remainder.asm | MSFT \r
   Ia32/DivU64x32Remainder.c | MSFT \r
   Ia32/DivU64x32.c | MSFT \r
   Ia32/DisablePaging32.c | MSFT \r
@@ -158,6 +154,10 @@
   Ia32/CpuId.c | MSFT \r
   Ia32/CpuBreakpoint.c | MSFT \r
   Ia32/ARShiftU64.c | MSFT \r
+  Ia32/Thunk16.asm | MSFT\r
+  Ia32/EnablePaging64.asm | MSFT\r
+  Ia32/EnableCache.c | MSFT\r
+  Ia32/DisableCache.c | MSFT\r
   SynchronizationMsc.c  | MSFT\r
 \r
   Ia32/Wbinvd.asm | INTEL \r
@@ -252,11 +252,12 @@
   Ia32/CpuId.asm | INTEL \r
   Ia32/CpuBreakpoint.asm | INTEL \r
   Ia32/ARShiftU64.asm | INTEL \r
+  Ia32/Thunk16.asm | INTEL\r
+  Ia32/EnablePaging64.asm | INTEL\r
+  Ia32/EnableCache.asm | INTEL\r
+  Ia32/DisableCache.asm | INTEL\r
   Synchronization.c | INTEL\r
 \r
-  Ia32/Thunk16.asm\r
-  Ia32/EnablePaging64.asm\r
-\r
   Ia32/Thunk16.S | GCC \r
   Ia32/CpuBreakpoint.S | GCC \r
   Ia32/CpuPause.S | GCC \r
@@ -351,26 +352,28 @@
   Ia32/ARShiftU64.S | GCC \r
   Ia32/RShiftU64.S | GCC \r
   Ia32/LShiftU64.S | GCC \r
+  Ia32/EnableCache.S | GCC\r
+  Ia32/DisableCache.S | GCC\r
   SynchronizationGcc.c  | GCC\r
 \r
   Ia32/DivS64x64Remainder.c\r
   Ia32/InternalSwitchStack.c\r
   Ia32/Non-existing.c\r
   Unaligned.c\r
-  x86WriteIdtr.c\r
-  x86WriteGdtr.c\r
-  x86Thunk.c\r
-  x86ReadIdtr.c\r
-  x86ReadGdtr.c\r
-  x86Msr.c\r
-  x86MemoryFence.c\r
-  x86GetInterruptState.c\r
-  x86FxSave.c\r
-  x86FxRestore.c\r
-  x86EnablePaging64.c\r
-  x86EnablePaging32.c\r
-  x86DisablePaging64.c\r
-  x86DisablePaging32.c\r
+  X86WriteIdtr.c\r
+  X86WriteGdtr.c\r
+  X86Thunk.c\r
+  X86ReadIdtr.c\r
+  X86ReadGdtr.c\r
+  X86Msr.c\r
+  X86MemoryFence.c\r
+  X86GetInterruptState.c\r
+  X86FxSave.c\r
+  X86FxRestore.c\r
+  X86EnablePaging64.c\r
+  X86EnablePaging32.c\r
+  X86DisablePaging64.c\r
+  X86DisablePaging32.c\r
 \r
 [Sources.X64]\r
   X64/Thunk16.asm\r
@@ -450,6 +453,8 @@
   X64/SwitchStack.asm\r
   X64/InterlockedCompareExchange64.asm \r
   X64/InterlockedCompareExchange32.asm \r
+  X64/EnableCache.asm\r
+  X64/DisableCache.asm\r
 \r
   X64/InterlockedDecrement.c | MSFT \r
   X64/InterlockedIncrement.c | MSFT \r
@@ -468,20 +473,20 @@
   X64/Non-existing.c\r
   Math64.c\r
   Unaligned.c\r
-  x86WriteIdtr.c\r
-  x86WriteGdtr.c\r
-  x86Thunk.c\r
-  x86ReadIdtr.c\r
-  x86ReadGdtr.c\r
-  x86Msr.c\r
-  x86MemoryFence.c\r
-  x86GetInterruptState.c\r
-  x86FxSave.c\r
-  x86FxRestore.c\r
-  x86EnablePaging64.c\r
-  x86EnablePaging32.c\r
-  x86DisablePaging64.c\r
-  x86DisablePaging32.c\r
+  X86WriteIdtr.c\r
+  X86WriteGdtr.c\r
+  X86Thunk.c\r
+  X86ReadIdtr.c\r
+  X86ReadGdtr.c\r
+  X86Msr.c\r
+  X86MemoryFence.c\r
+  X86GetInterruptState.c\r
+  X86FxSave.c\r
+  X86FxRestore.c\r
+  X86EnablePaging64.c\r
+  X86EnablePaging32.c\r
+  X86DisablePaging64.c\r
+  X86DisablePaging32.c\r
   X64/WriteMsr64.S | GCC \r
   X64/WriteMm7.S | GCC \r
   X64/WriteMm6.S | GCC \r
@@ -565,9 +570,12 @@
   X64/CpuIdEx.S | GCC \r
   X64/CpuBreakpoint.S | GCC \r
   SynchronizationGcc.c  | GCC \r
+  X64/EnableCache.S | GCC\r
+  X64/DisableCache.S | GCC\r
   ChkStkGcc.c  | GCC \r
 \r
 [Sources.IPF]\r
+  Ipf/AsmCpuMisc.s\r
   Ipf/AccessGp.s\r
   Ipf/ReadCpuid.s\r
   Ipf/ExecFc.s\r
@@ -589,11 +597,14 @@
   Ipf/CpuBreakpointMsc.c | MSFT\r
   Ipf/Unaligned.c\r
   Ipf/SwitchStack.s\r
-  Ipf/longjmp.s\r
-  Ipf/setjmp.s\r
-  Ipf/PalCallStatic.s\r
-  Ipf/ia_64gen.h\r
-  Ipf/asm.h\r
+  Ipf/LongJmp.s\r
+  Ipf/SetJmp.s\r
+  Ipf/ReadCr.s\r
+  Ipf/ReadControlRegister.c\r
+  Ipf/ReadAr.s\r
+  Ipf/ReadApplicationRegister.c\r
+  Ipf/Ia64gen.h\r
+  Ipf/Asm.h\r
   Math64.c\r
   Synchronization.c     | INTEL \r
   SynchronizationMsc.c  | MSFT \r