MdePkg BaseLib: Fix GCC build break

[mirror_edk2.git] / MdePkg / Library / BaseLib / BaseLibInternals.h

diff --git a/MdePkg/Library/BaseLib/BaseLibInternals.h b/MdePkg/Library/BaseLib/BaseLibInternals.h
index 19ed01beda74e15081368f4903012cf97d44fb30..a6e6e9950941a146e224be93b2a22bdb264ed6d1 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLibInternals.h
+++ b/MdePkg/Library/BaseLib/BaseLibInternals.h
@@ -1,8 +1,8 @@
 /** @file\r
   Declaration of internal functions in BaseLib.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
-  All rights reserved. This program and the accompanying materials\r
+  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   http://opensource.org/licenses/bsd-license.php\r
@@ -735,15 +735,6 @@ InternalX86DisablePaging64 (
 // IPF specific functions\r
 //\r
 \r
-//\r
-// Structure definition for look up table.\r
-//\r
-typedef struct {\r
-  UINT64 Index;\r
-  UINT64 (*Function) (VOID);\r
-} REGISTER_ENTRY;\r
-\r
-\r
 /**\r
   Reads control register DCR.\r
 \r
@@ -1625,6 +1616,38 @@ AsmSwitchStackAndBackingStore (
   IN      VOID                      *NewStack,\r
   IN      VOID                      *NewBsp\r
   );\r
+\r
+/**\r
+  Internal worker function to invalidate a range of instruction cache lines\r
+  in the cache coherency domain of the calling CPU.\r
+\r
+  Internal worker function to invalidate the instruction cache lines specified\r
+  by Address and Length. If Address is not aligned on a cache line boundary,\r
+  then entire instruction cache line containing Address is invalidated. If\r
+  Address + Length is not aligned on a cache line boundary, then the entire\r
+  instruction cache line containing Address + Length -1 is invalidated. This\r
+  function may choose to invalidate the entire instruction cache if that is more\r
+  efficient than invalidating the specified range. If Length is 0, the no instruction\r
+  cache lines are invalidated. Address is returned.\r
+  This function is only available on IPF.\r
+\r
+  @param  Address The base address of the instruction cache lines to\r
+                  invalidate. If the CPU is in a physical addressing mode, then\r
+                  Address is a physical address. If the CPU is in a virtual\r
+                  addressing mode, then Address is a virtual address.\r
+\r
+  @param  Length  The number of bytes to invalidate from the instruction cache.\r
+\r
+  @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InternalFlushCacheRange (\r
+  IN      VOID                      *Address,\r
+  IN      UINTN                     Length\r
+  );\r
+\r
 #else\r
 \r
 #endif\r