/** @file\r
Declaration of internal functions in BaseLib.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
-#include <Library/TimerLib.h>\r
#include <Library/PcdLib.h>\r
\r
//\r
IN CONST LIST_ENTRY *Node\r
);\r
\r
-\r
-/**\r
- Performs an atomic increment of an 32-bit unsigned integer.\r
-\r
- Performs an atomic increment of the 32-bit unsigned integer specified by\r
- Value and returns the incremented value. The increment operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- @param Value A pointer to the 32-bit value to increment.\r
-\r
- @return The incremented value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InternalSyncIncrement (\r
- IN volatile UINT32 *Value\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic decrement of an 32-bit unsigned integer.\r
-\r
- Performs an atomic decrement of the 32-bit unsigned integer specified by\r
- Value and returns the decrement value. The decrement operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- @param Value A pointer to the 32-bit value to decrement.\r
-\r
- @return The decrement value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InternalSyncDecrement (\r
- IN volatile UINT32 *Value\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
-\r
- Performs an atomic compare exchange operation on the 32-bit unsigned integer\r
- specified by Value. If Value is equal to CompareValue, then Value is set to\r
- ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,\r
- then Value is returned. The compare exchange operation must be performed using\r
- MP safe mechanisms.\r
-\r
- @param Value A pointer to the 32-bit value for the compare exchange\r
- operation.\r
- @param CompareValue 32-bit value used in compare operation.\r
- @param ExchangeValue 32-bit value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InternalSyncCompareExchange32 (\r
- IN volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
-\r
- Performs an atomic compare exchange operation on the 64-bit unsigned integer specified\r
- by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and\r
- CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.\r
- The compare exchange operation must be performed using MP safe mechanisms.\r
-\r
- @param Value A pointer to the 64-bit value for the compare exchange\r
- operation.\r
- @param CompareValue 64-bit value used in compare operation.\r
- @param ExchangeValue 64-bit value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-InternalSyncCompareExchange64 (\r
- IN volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
- );\r
-\r
-\r
/**\r
Worker function that returns a bit field from Operand.\r
\r
// IPF specific functions\r
//\r
\r
-//\r
-// Structure definition for look up table.\r
-//\r
-typedef struct {\r
- UINT64 Index;\r
- UINT64 (*Function) (VOID);\r
-} REGISTER_ENTRY;\r
-\r
-\r
/**\r
Reads control register DCR.\r
\r
IN VOID *NewStack,\r
IN VOID *NewBsp\r
);\r
+\r
+/**\r
+ Internal worker function to invalidate a range of instruction cache lines\r
+ in the cache coherency domain of the calling CPU.\r
+\r
+ Internal worker function to invalidate the instruction cache lines specified\r
+ by Address and Length. If Address is not aligned on a cache line boundary,\r
+ then entire instruction cache line containing Address is invalidated. If\r
+ Address + Length is not aligned on a cache line boundary, then the entire\r
+ instruction cache line containing Address + Length -1 is invalidated. This\r
+ function may choose to invalidate the entire instruction cache if that is more\r
+ efficient than invalidating the specified range. If Length is 0, the no instruction\r
+ cache lines are invalidated. Address is returned.\r
+ This function is only available on IPF.\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InternalFlushCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r
#else\r
\r
#endif\r
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