#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2006 - 2009, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
+# http://opensource.org/licenses/bsd-license.php.\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
#include <Library/BaseLib.h>\r
\r
-.globl ASM_PFX(m16Start)\r
-.globl ASM_PFX(m16Size)\r
-.globl ASM_PFX(mThunk16Attr)\r
-.globl ASM_PFX(m16Gdt)\r
-.globl ASM_PFX(m16GdtrBase)\r
-.globl ASM_PFX(mTransition)\r
-.globl ASM_PFX(InternalAsmThunk16)\r
+ASM_GLOBAL ASM_PFX(m16Start)\r
+ASM_GLOBAL ASM_PFX(m16Size)\r
+ASM_GLOBAL ASM_PFX(mThunk16Attr)\r
+ASM_GLOBAL ASM_PFX(m16Gdt)\r
+ASM_GLOBAL ASM_PFX(m16GdtrBase)\r
+ASM_GLOBAL ASM_PFX(mTransition)\r
+ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
\r
# define the structure of IA32_REGS\r
-.equ _EDI, 0 #size 4\r
-.equ _ESI, 4 #size 4\r
-.equ _EBP, 8 #size 4\r
-.equ _ESP, 12 #size 4\r
-.equ _EBX, 16 #size 4\r
-.equ _EDX, 20 #size 4\r
-.equ _ECX, 24 #size 4\r
-.equ _EAX, 28 #size 4\r
-.equ _DS, 32 #size 2\r
-.equ _ES, 34 #size 2\r
-.equ _FS, 36 #size 2\r
-.equ _GS, 38 #size 2\r
-.equ _EFLAGS, 40 #size 8\r
-.equ _EIP, 48 #size 4\r
-.equ _CS, 52 #size 2\r
-.equ _SS, 54 #size 2\r
-.equ IA32_REGS_SIZE, 56\r
+.set _EDI, 0 #size 4\r
+.set _ESI, 4 #size 4\r
+.set _EBP, 8 #size 4\r
+.set _ESP, 12 #size 4\r
+.set _EBX, 16 #size 4\r
+.set _EDX, 20 #size 4\r
+.set _ECX, 24 #size 4\r
+.set _EAX, 28 #size 4\r
+.set _DS, 32 #size 2\r
+.set _ES, 34 #size 2\r
+.set _FS, 36 #size 2\r
+.set _GS, 38 #size 2\r
+.set _EFLAGS, 40 #size 8\r
+.set _EIP, 48 #size 4\r
+.set _CS, 52 #size 2\r
+.set _SS, 54 #size 2\r
+.set IA32_REGS_SIZE, 56\r
\r
.data\r
\r
# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
# by user code. It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
-.globl ASM_PFX(BackFromUserCode)\r
+ASM_GLOBAL ASM_PFX(BackFromUserCode)\r
ASM_PFX(BackFromUserCode):\r
#\r
# The order of saved registers on the stack matches the order they appears\r
SavedCr0: .space 4\r
movq %rax, %cr0\r
.byte 0x66,0xea # jmp far cs:L_64Bit\r
-L_64Eip: .space 4\r
+L_64Eip: .space 4\r
SavedCs: .space 2\r
L_64BitCode: \r
- movq %r8, %rsp\r
+ .byte 0x90\r
+ .byte 0x67,0xbc # mov esp, imm32\r
+SavedSp: .space 4 # restore stack\r
+ nop\r
ret\r
\r
_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
# _ToUserCode() takes control in real mode before passing control to user code.\r
# It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
-.globl ASM_PFX(ToUserCode)\r
+ASM_GLOBAL ASM_PFX(ToUserCode)\r
ASM_PFX(ToUserCode):\r
movl %edx,%ss # set new segment selectors\r
movl %edx,%ds\r
movl $0xc0000080,%ecx\r
movq %rax, %cr0\r
rdmsr\r
- andb $0b11111110, %ah \r
+ andb $0xfe, %ah # $0b11111110\r
wrmsr\r
movq %rbp, %cr4\r
movl %esi,%ss # set up 16-bit stack segment\r
.byte 0x66 # make the following retf 32-bit\r
lret # transfer control to user code\r
\r
-.equ CODE16, ASM_PFX(_16Code) - .\r
-.equ DATA16, ASM_PFX(_16Data) - .\r
-.equ DATA32, ASM_PFX(_32Data) - .\r
+.set CODE16, ASM_PFX(_16Code) - .\r
+.set DATA16, ASM_PFX(_16Data) - .\r
+.set DATA32, ASM_PFX(_32Data) - .\r
\r
ASM_PFX(NullSeg): .quad 0\r
ASM_PFX(_16Code):\r
.byte 0xcf # 16-bit segment, 4GB limit\r
.byte 0\r
\r
-.equ GDT_SIZE, . - ASM_PFX(NullSeg)\r
+.set GDT_SIZE, . - ASM_PFX(NullSeg)\r
\r
#------------------------------------------------------------------------------\r
# IA32_REGISTER_SET *\r
# IN OUT VOID *Transition\r
# );\r
#------------------------------------------------------------------------------\r
-# MISMATCH: "InternalAsmThunk16 PROC USES rbp rbx rsi rdi"\r
\r
-.globl ASM_PFX(InternalAsmThunk16)\r
+ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
ASM_PFX(InternalAsmThunk16):\r
pushq %rbp\r
pushq %rbx\r
pushq %rsi\r
pushq %rdi\r
\r
- movl %ds, %r10d # r9 ~ r11 are not accessible in 16-bit\r
- movl %es, %r11d # so use them for saving seg registers\r
- movl %ss, %r9d\r
+ movl %ds, %ebx\r
+ pushq %rbx # Save ds segment register on the stack\r
+ movl %es, %ebx\r
+ pushq %rbx # Save es segment register on the stack\r
+ movl %ss, %ebx\r
+ pushq %rbx # Save ss segment register on the stack\r
+\r
.byte 0x0f, 0xa0 #push fs\r
.byte 0x0f, 0xa8 #push gs\r
movq %rcx, %rsi\r
movl %edx,%eax # eax <- transition code address\r
andl $0xf,%edx\r
shll $12,%eax # segment address in high order 16 bits\r
- lea (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax\r
+ lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%rdx), %ax\r
stosl # [edi] <- return address of user code\r
- sgdt (SavedGdt - SavedCr4)(%rcx) \r
- sidt 0x38(%rsp)\r
+ sgdt 0x60(%rsp) # save GDT stack in argument space\r
+ movzwq 0x60(%rsp), %r10 # r10 <- GDT limit \r
+ lea ((ASM_PFX(InternalAsmThunk16) - SavedCr4) + 0xf)(%rcx), %r11 \r
+ andq $0xfffffffffffffff0, %r11 # r11 <- 16-byte aligned shadowed GDT table in real mode buffer \r
+ \r
+ movw %r10w, (SavedGdt - SavedCr4)(%rcx) # save the limit of shadowed GDT table\r
+ movq %r11, (SavedGdt - SavedCr4 + 0x2)(%rcx) # save the base address of shadowed GDT table\r
+ \r
+ movq 0x62(%rsp) ,%rsi # rsi <- the original GDT base address\r
+ xchg %r10, %rcx # save rcx to r10 and initialize rcx to be the limit of GDT table \r
+ incq %rcx # rcx <- the size of memory to copy\r
+ xchg %r11, %rdi # save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
+ rep\r
+ movsb # perform memory copy to shadow GDT table\r
+ movq %r10, %rcx # restore the orignal rcx before memory copy\r
+ movq %r11, %rdi # restore the original rdi before memory copy\r
+ \r
+ sidt 0x50(%rsp)\r
movq %cr0, %rax\r
movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r
andl $0x7ffffffe,%eax # clear PE, PG bits\r
movl %edx,%ss\r
pushfq\r
lea -8(%rdx), %edx\r
- lea L_RetFromRealMode, %r8\r
+ lea L_RetFromRealMode(%rip), %r8\r
pushq %r8\r
movl %cs, %r8d\r
movw %r8w, (SavedCs - SavedCr4)(%rcx)\r
- movq %rsp, %r8\r
+ movl %esp, (SavedSp - SavedCr4)(%rcx)\r
.byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r
.byte _EntryPoint - SavedCr4\r
L_RetFromRealMode: \r
popfq\r
- lidt 0x38(%rsp)\r
+ lgdt 0x60(%rsp) # restore protected mode GDTR\r
+ lidt 0x50(%rsp) # restore protected mode IDTR\r
lea -IA32_REGS_SIZE(%rbp), %eax\r
.byte 0x0f, 0xa9 # pop gs\r
.byte 0x0f, 0xa1 # pop fs\r
- movl %r9d, %ss\r
- movl %r11d, %es\r
- movl %r10d, %ds\r
+ \r
+ popq %rbx\r
+ movl %ebx, %ss\r
+ popq %rbx\r
+ movl %ebx, %es\r
+ popq %rbx\r
+ movl %ebx, %ds\r
\r
popq %rdi\r
popq %rsi\r
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