All assertions for I/O operations are handled in MMIO functions in the IoLib\r
Library.\r
\r
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
-\r
/**\r
Assert the validity of a PCI address. A valid PCI address should contain 1's\r
- only in the low 28 bits.\r
+ only in the low 28 bits. PcdPciExpressBaseSize limits the size to the real\r
+ number of PCI busses in this segment.\r
\r
@param A The address to validate.\r
\r
ASSERT (((A) & ~0xfffffff) == 0)\r
\r
/**\r
- Registers a PCI device so PCI configuration registers may be accessed after \r
+ Registers a PCI device so PCI configuration registers may be accessed after\r
SetVirtualAddressMap().\r
- \r
- Registers the PCI device specified by Address so all the PCI configuration \r
- registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r
+\r
+ Registers the PCI device specified by Address so all the PCI configuration\r
+ registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r
is called.\r
- \r
+\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- \r
+\r
@retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
after ExitBootServices().\r
@retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
at runtime could not be mapped.\r
\r
/**\r
Gets the base address of PCI Express.\r
- \r
+\r
This internal functions retrieves PCI Express Base Address via a PCD entry\r
PcdPciExpressBaseAddress.\r
- \r
+\r
@return The base address of PCI Express.\r
\r
**/\r
-VOID*\r
+VOID *\r
GetPciExpressBaseAddress (\r
VOID\r
)\r
{\r
- return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r
+ return (VOID *)(UINTN)PcdGet64 (PcdPciExpressBaseAddress);\r
+}\r
+\r
+/**\r
+ Gets the size of PCI Express.\r
+\r
+ This internal functions retrieves PCI Express Base Size via a PCD entry\r
+ PcdPciExpressBaseSize.\r
+\r
+ @return The base size of PCI Express.\r
+\r
+**/\r
+STATIC\r
+UINTN\r
+PcdPciExpressBaseSize (\r
+ VOID\r
+ )\r
+{\r
+ return (UINTN)PcdGet64 (PcdPciExpressBaseSize);\r
}\r
\r
/**\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
- @return The read value from the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The read value from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioRead8 ((UINTN)GetPciExpressBaseAddress () + Address);\r
}\r
\r
/**\r
Register.\r
@param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioWrite8 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r
}\r
\r
/**\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioOr8 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r
}\r
\r
/**\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioAnd8 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r
}\r
\r
/**\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioAndThenOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
AndData,\r
OrData\r
);\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..7.\r
\r
- @return The value of the bit field read from the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value of the bit field read from the PCI configuration\r
+ register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldRead8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit\r
);\r
Range 0..7.\r
@param Value The new value of the bit field.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldWrite8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
Value\r
Range 0..7.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
OrData\r
Range 0..7.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldAnd8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldAndThenOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData,\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
- @return The read value from the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The read value from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioRead16 ((UINTN)GetPciExpressBaseAddress () + Address);\r
}\r
\r
/**\r
Register.\r
@param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioWrite16 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r
}\r
\r
/**\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioOr16 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r
}\r
\r
/**\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioAnd16 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r
}\r
\r
/**\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioAndThenOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
AndData,\r
OrData\r
);\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..15.\r
\r
- @return The value of the bit field read from the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value of the bit field read from the PCI configuration\r
+ register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldRead16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit\r
);\r
Range 0..15.\r
@param Value The new value of the bit field.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldWrite16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
Value\r
Range 0..15.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
OrData\r
Range 0..15.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldAnd16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldAndThenOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData,\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
- @return The read value from the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The read value from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioRead32 ((UINTN)GetPciExpressBaseAddress () + Address);\r
}\r
\r
/**\r
Register.\r
@param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioWrite32 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r
}\r
\r
/**\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioOr32 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r
}\r
\r
/**\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioAnd32 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r
}\r
\r
/**\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioAndThenOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
AndData,\r
OrData\r
);\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..31.\r
\r
- @return The value of the bit field read from the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value of the bit field read from the PCI\r
+ configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldRead32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit\r
);\r
Range 0..31.\r
@param Value The new value of the bit field.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldWrite32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
Value\r
Range 0..31.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
OrData\r
Range 0..31.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldAnd32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldAndThenOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData,\r
@param Size The size in bytes of the transfer.\r
@param Buffer The pointer to a buffer receiving the data read.\r
\r
- @return Size read data from StartAddress.\r
+ @retval (UINTN)-1 Invalid PCI address.\r
+ @retval other Size read data from StartAddress.\r
\r
**/\r
UINTN\r
EFIAPI\r
PciExpressReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
+ if (StartAddress >= PcdPciExpressBaseSize ()) {\r
+ return (UINTN)-1;\r
+ }\r
+\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Read as many double words as possible\r
//\r
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));\r
\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Read the last remaining word if exist\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
@param Size The size in bytes of the transfer.\r
@param Buffer The pointer to a buffer containing the data to write.\r
\r
- @return Size written to StartAddress.\r
+ @retval (UINTN)-1 Invalid PCI address.\r
+ @retval other Size written to StartAddress.\r
\r
**/\r
UINTN\r
EFIAPI\r
PciExpressWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
+ if (StartAddress >= PcdPciExpressBaseSize ()) {\r
+ return (UINTN)-1;\r
+ }\r
+\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Write as many double words as possible\r
//\r
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Write the last remaining word if exist\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
projects / mirror_edk2.git / blobdiff