+++ /dev/null
-/** @file\r
- PCI Library using PC Express access.\r
-\r
- Copyright (c) 2006, Intel Corporation<BR>\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- Module Name: PciLib.c\r
-\r
-**/\r
-\r
-/**\r
- Reads an 8-bit PCI configuration register.\r
-\r
- Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciRead8 (\r
- IN UINTN Address\r
- )\r
-{\r
- return PciExpressRead8 (Address);\r
-}\r
-\r
-/**\r
- Writes an 8-bit PCI configuration register.\r
-\r
- Writes the 8-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Data\r
- )\r
-{\r
- return PciExpressWrite8 (Address, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r
- an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciExpressOr8 (Address, OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciExpressAnd8 (Address, AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise inclusive OR with another 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciExpressAndThenOr8 (Address, AndData, OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 8-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 8-bit register.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r
-}\r
-\r
-/**\r
- Reads a 16-bit PCI configuration register.\r
-\r
- Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciRead16 (\r
- IN UINTN Address\r
- )\r
-{\r
- return PciExpressRead16 (Address);\r
-}\r
-\r
-/**\r
- Writes a 16-bit PCI configuration register.\r
-\r
- Writes the 16-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Data\r
- )\r
-{\r
- return PciExpressWrite16 (Address, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r
- a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciExpressOr16 (Address, OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciExpressAnd16 (Address, AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise inclusive OR with another 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciExpressAndThenOr16 (Address, AndData, OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 16-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r
-}\r
-\r
-/**\r
- Reads a 32-bit PCI configuration register.\r
-\r
- Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciRead32 (\r
- IN UINTN Address\r
- )\r
-{\r
- return PciExpressRead32 (Address);\r
-}\r
-\r
-/**\r
- Writes a 32-bit PCI configuration register.\r
-\r
- Writes the 32-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Data\r
- )\r
-{\r
- return PciExpressWrite32 (Address, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r
- a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciExpressOr32 (Address, OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciExpressAnd32 (Address, AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise inclusive OR with another 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciExpressAndThenOr32 (Address, AndData, OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 32-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 32-bit register.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r
-}\r
-\r
-/**\r
- Reads a range of PCI configuration registers into a caller supplied buffer.\r
-\r
- Reads the range of PCI configuration registers specified by StartAddress and\r
- Size into the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be read. Size is\r
- returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
- and 16-bit PCI configuration read cycles may be used at the beginning and the\r
- end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return PciExpressReadBuffer (StartAddress, Size, Buffer);\r
-}\r
-\r
-/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI\r
- configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress and\r
- Size from the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be written. Size is\r
- returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
- and the end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r
-}\r