All assertions for I/O operations are handled in MMIO functions in the IoLib\r
Library.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
\r
#include <PiDxe.h>\r
\r
+#include <Guid/EventGroup.h>\r
+\r
#include <Library/BaseLib.h>\r
#include <Library/PciExpressLib.h>\r
#include <Library/IoLib.h>\r
EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r
\r
///\r
-/// Module global that contains the base physical address of the PCI Express MMIO range\r
+/// Module global that contains the base physical address of the PCI Express MMIO range.\r
///\r
UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r
\r
///\r
-/// The number of PCI devices that have been registered for runtime access\r
+/// The number of PCI devices that have been registered for runtime access.\r
///\r
UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r
\r
///\r
-/// The table of PCI devices that have been registered for runtime access\r
+/// The table of PCI devices that have been registered for runtime access.\r
///\r
PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE *mDxeRuntimePciExpressLibRegistrationTable = NULL;\r
\r
///\r
-/// The table index of the most recent virtual address lookup\r
+/// The table index of the most recent virtual address lookup.\r
///\r
UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r
\r
Convert the physical PCI Express MMIO addresses for all registered PCI devices\r
to virtual addresses.\r
\r
- @param[in] Event The Event that is being processed\r
- @param[in] Context Event Context\r
+ @param[in] Event The event that is being processed.\r
+ @param[in] Context The Event Context.\r
**/\r
VOID\r
EFIAPI\r
}\r
\r
/**\r
- The constructor function caches the PCI Express Base Address and creates a \r
+ The constructor function caches the PCI Express Base Address and creates a\r
Set Virtual Address Map event to convert physical address to virtual addresses.\r
- \r
+\r
@param ImageHandle The firmware allocated handle for the EFI image.\r
@param SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The constructor completed successfully.\r
@retval Other value The constructor did not complete successfully.\r
\r
//\r
// Register SetVirtualAddressMap () notify function\r
//\r
- Status = gBS->CreateEvent (\r
- EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE,\r
+ Status = gBS->CreateEventEx (\r
+ EVT_NOTIFY_SIGNAL,\r
TPL_NOTIFY,\r
DxeRuntimePciExpressLibVirtualNotify,\r
NULL,\r
+ &gEfiEventVirtualAddressChangeGuid,\r
&mDxeRuntimePciExpressLibVirtualNotifyEvent\r
);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
/**\r
- The destructor function frees any allocated buffers and closes the Set Virtual \r
+ The destructor function frees any allocated buffers and closes the Set Virtual\r
Address Map event.\r
- \r
+\r
@param ImageHandle The firmware allocated handle for the EFI image.\r
@param SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The destructor completed successfully.\r
@retval Other value The destructor did not complete successfully.\r
\r
EFI_STATUS Status;\r
\r
//\r
- // If one or more PCI devices have been registered for runtime access, then \r
+ // If one or more PCI devices have been registered for runtime access, then\r
// free the registration table.\r
//\r
if (mDxeRuntimePciExpressLibRegistrationTable != NULL) {\r
\r
/**\r
Gets the base address of PCI Express.\r
- \r
+\r
This internal functions retrieves PCI Express Base Address via a PCD entry\r
PcdPciExpressBaseAddress.\r
- \r
- @return The base address of PCI Express.\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and Register.\r
+ @return The base address of PCI Express.\r
\r
**/\r
UINTN\r
//\r
// See if there is a physical address match at the exact same index as the last address match\r
//\r
- if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & 0x0ffff000)) {\r
+ if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & (~0x00000fff))) {\r
//\r
// Convert the physical address to a virtual address and return the virtual address\r
//\r
}\r
\r
//\r
- // Search the entire table for a phyical address match\r
+ // Search the entire table for a physical address match\r
//\r
for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
- if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & 0x0ffff000)) {\r
+ if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & (~0x00000fff))) {\r
//\r
// Cache the matching index value\r
//\r
CpuBreakpoint();\r
\r
//\r
- // Return the physical address \r
+ // Return the physical address\r
//\r
return Address;\r
}\r
\r
/**\r
- Registers a PCI device so PCI configuration registers may be accessed after \r
+ Registers a PCI device so PCI configuration registers may be accessed after\r
SetVirtualAddressMap().\r
- \r
- Registers the PCI device specified by Address so all the PCI configuration \r
- registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r
+\r
+ Registers the PCI device specified by Address so all the PCI configuration\r
+ registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r
is called.\r
- \r
+\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- \r
+\r
@retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
after ExitBootServices().\r
@retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
at runtime could not be mapped.\r
// Grow the size of the registration table\r
//\r
NewTable = ReallocateRuntimePool (\r
- (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r
- (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r
+ (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE),\r
+ (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE),\r
mDxeRuntimePciExpressLibRegistrationTable\r
);\r
if (NewTable == NULL) {\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@return The read value from the PCI configuration register.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param Value The value to write.\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address PCI configuration register to read.\r
+ @param Address The PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..7.\r
- @param Value New value of the bit field.\r
+ @param Value The new value of the bit field.\r
\r
@return The value written back to the PCI configuration register.\r
\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@return The read value from the PCI configuration register.\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param Value The value to write.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address PCI configuration register to read.\r
+ @param Address The PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..15.\r
- @param Value New value of the bit field.\r
+ @param Value The new value of the bit field.\r
\r
@return The value written back to the PCI configuration register.\r
\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@return The read value from the PCI configuration register.\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param Value The value to write.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address PCI configuration register to read.\r
+ @param Address The PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..31.\r
- @param Value New value of the bit field.\r
+ @param Value The new value of the bit field.\r
\r
@return The value written back to the PCI configuration register.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer receiving the data read.\r
\r
@return Size read data from StartAddress.\r
\r
{\r
UINTN ReturnValue;\r
\r
+ //\r
+ // Make sure Address is valid\r
+ //\r
+ ASSERT (((StartAddress) & ~0xfffffff) == 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer containing the data to write.\r
\r
@return Size written to StartAddress.\r
\r
{\r
UINTN ReturnValue;\r
\r
+ //\r
+ // Make sure Address is valid\r
+ //\r
+ ASSERT (((StartAddress) & ~0xfffffff) == 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
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