/** @file\r
PCI Segment Library implementation using PCI CFG2 PPI.\r
\r
- Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of\r
- the BSD License which accompanies this distribution. The full\r
- text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
- \r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \\r
ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
\r
/**\r
\r
This internal function retrieves PCI CFG2 PPI from PPI database.\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function and Register.\r
+ @param Address The address that encodes the PCI Segment, Bus, Device,\r
+ Function and Register.\r
\r
@return The pointer to PCI CFG2 PPI.\r
\r
**/\r
EFI_PEI_PCI_CFG2_PPI *\r
InternalGetPciCfg2Ppi (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Instance;\r
- EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 SegmentNumber;\r
+ EFI_STATUS Status;\r
+ UINTN Instance;\r
+ EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 SegmentNumber;\r
\r
Instance = 0;\r
PciCfg2Ppi = NULL;\r
// Loop through all instances of the PPI and match segment number\r
//\r
do {\r
- Status = PeiServicesLocatePpi(\r
+ Status = PeiServicesLocatePpi (\r
&gEfiPciCfg2PpiGuid,\r
Instance,\r
NULL,\r
- (VOID**) &PciCfg2Ppi\r
+ (VOID **)&PciCfg2Ppi\r
);\r
ASSERT_EFI_ERROR (Status);\r
Instance++;\r
\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- @param Width Width of data to read\r
+ @param Width The width of data to read\r
\r
@return The value read from the PCI configuration register.\r
\r
**/\r
UINT32\r
PeiPciSegmentLibPciCfg2ReadWorker (\r
- IN UINT64 Address,\r
- IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r
+ IN UINT64 Address,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r
)\r
{\r
- UINT32 Data;\r
- CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 PciCfg2Address;\r
+ UINT32 Data;\r
+ CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 PciCfg2Address;\r
\r
- PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
+ PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r
PciCfg2Ppi->Read (\r
GetPeiServicesTablePointer (),\r
\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- @param Width Width of data to write\r
+ @param Width The width of data to write\r
@param Data The value to write.\r
\r
@return The value written to the PCI configuration register.\r
**/\r
UINT32\r
PeiPciSegmentLibPciCfg2WriteWorker (\r
- IN UINT64 Address,\r
- IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
- IN UINT32 Data\r
+ IN UINT64 Address,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT32 Data\r
)\r
{\r
- CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 PciCfg2Address;\r
+ CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 PciCfg2Address;\r
\r
- PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
+ PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r
PciCfg2Ppi->Write (\r
GetPeiServicesTablePointer (),\r
}\r
\r
/**\r
- Register a PCI device so PCI configuration registers may be accessed after \r
+ Register a PCI device so PCI configuration registers may be accessed after\r
SetVirtualAddressMap().\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
+ @param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
- \r
+\r
@retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
after ExitBootServices().\r
@retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
at runtime could not be mapped.\r
\r
Reads and returns the 8-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
- \r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
@return The 8-bit PCI configuration register specified by Address.\r
\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
\r
- return (UINT8) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r
+ return (UINT8)PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r
}\r
\r
/**\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
\r
@return The value written to the PCI configuration register.\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
\r
- return (UINT8) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r
+ return (UINT8)PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r
}\r
\r
/**\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) | OrData));\r
}\r
\r
/**\r
This function must guarantee that all PCI read and write operations are serialized.\r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));\r
}\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
followed a bitwise OR with another 8-bit value.\r
- \r
+\r
Reads the 8-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to read.\r
+ @param Address PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..7.\r
- @param Value The new value of the bit field.\r
+ @param Value New value of the bit field.\r
\r
@return The value written back to the PCI configuration register.\r
\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciSegmentWrite8 (\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciSegmentWrite8 (\r
\r
/**\r
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
bitwise AND followed by a bitwise OR between the read result and\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
\r
Reads and returns the 16-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- \r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
@return The 16-bit PCI configuration register specified by Address.\r
\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
\r
- return (UINT16) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r
+ return (UINT16)PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r
}\r
\r
/**\r
\r
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
\r
@return The parameter of Value.\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
\r
- return (UINT16) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r
+ return (UINT16)PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r
}\r
\r
/**\r
a 16-bit value.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
+ bitwise OR between the read result and the value specified by OrData, and\r
+ writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned. This function\r
+ must guarantee that all PCI read and write operations are serialized.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function and\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) | OrData));\r
}\r
\r
/**\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- \r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) & AndData));\r
}\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
followed a bitwise OR with another 16-bit value.\r
- \r
+\r
Reads the 16-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to read.\r
+ @param Address PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..15.\r
- @param Value The new value of the bit field.\r
+ @param Value New value of the bit field.\r
\r
@return The value written back to the PCI configuration register.\r
\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciSegmentWrite16 (\r
}\r
\r
/**\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address. \r
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r
+ the result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
}\r
\r
/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r
- and writes the result back to the bit field in the 16-bit port.\r
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
+ AND, writes the result back to the bit field in the 16-bit register.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 16-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in OrData are stripped.\r
- \r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciSegmentWrite16 (\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
\r
Reads and returns the 32-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
@return The 32-bit PCI configuration register specified by Address.\r
\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
\r
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
\r
@return The parameter of Value.\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
followed a bitwise OR with another 32-bit value.\r
- \r
+\r
Reads the 32-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to read.\r
+ @param Address PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..31.\r
- @param Value The new value of the bit field.\r
+ @param Value New value of the bit field.\r
\r
@return The value written back to the PCI configuration register.\r
\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciSegmentWrite32 (\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
AND, and writes the result back to the bit field in the 32-bit register.\r
\r
- \r
+\r
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
AND between the read result and the value specified by AndData, and writes the result\r
to the 32-bit PCI configuration register specified by Address. The value written to\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
- \r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address The PCI configuration register to write.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
Function and Register.\r
- @param Size The size in bytes of the transfer.\r
- @param Buffer The pointer to a buffer receiving the data read.\r
+ @param Size Size in bytes of the transfer.\r
+ @param Buffer Pointer to a buffer receiving the data read.\r
\r
@return Size\r
\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
return ReturnValue;\r
}\r
\r
-\r
/**\r
Copies the data in a caller supplied buffer to a specified range of PCI\r
configuration space.\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
Function and Register.\r
- @param Size The size in bytes of the transfer.\r
- @param Buffer The pointer to a buffer containing the data to write.\r
+ @param Size Size in bytes of the transfer.\r
+ @param Buffer Pointer to a buffer containing the data to write.\r
\r
@return The parameter of Size.\r
\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
projects / mirror_edk2.git / blobdiff