Function headers in .h and .c files synchronized with spec

[mirror_edk2.git] / MdePkg / Library / PeiPciSegmentLibPciCfg2 / PciSegmentLib.c

diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
index 729391d9c995fa84094c6a123530223396558c1a..a02954ae0564fddbb4671d07a15e14e0a3a4e68e 100644 (file)
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
@@ -273,23 +273,19 @@ PciSegmentOr8 (
 }\r
 \r
 /**\r
-  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
-  value.\r
-\r
-  Reads the 8-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 8-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
 \r
+  Reads the 8-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  and writes the result to the 8-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
   If any reserved bits in Address are set, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT8\r
@@ -303,25 +299,23 @@ PciSegmentAnd8 (
 }\r
 \r
 /**\r
-  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
-  value, followed a  bitwise inclusive OR with another 8-bit value.\r
-\r
-  Reads the 8-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData,\r
-  performs a bitwise inclusive OR between the result of the AND operation and\r
-  the value specified by OrData, and writes the result to the 8-bit PCI\r
-  configuration register specified by Address. The value written to the PCI\r
-  configuration register is returned. This function must guarantee that all PCI\r
-  read and write operations are serialized.\r
-\r
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
+  followed a  bitwise inclusive OR with another 8-bit value.\r
+  \r
+  Reads the 8-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 8-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
-  @param  OrData  The value to OR with the result of the AND operation.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData    The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT8\r
@@ -617,23 +611,21 @@ PciSegmentOr16 (
 }\r
 \r
 /**\r
-  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
-  value.\r
-\r
-  Reads the 16-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 16-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
 \r
+  Reads the 16-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  and writes the result to the 16-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  \r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
-\r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT16\r
@@ -961,23 +953,21 @@ PciSegmentOr32 (
 }\r
 \r
 /**\r
-  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
-  value.\r
-\r
-  Reads the 32-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 32-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
 \r
+  Reads the 32-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  and writes the result to the 32-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT32\r
@@ -991,25 +981,24 @@ PciSegmentAnd32 (
 }\r
 \r
 /**\r
-  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
-  value, followed a  bitwise inclusive OR with another 32-bit value.\r
-\r
-  Reads the 32-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData,\r
-  performs a bitwise inclusive OR between the result of the AND operation and\r
-  the value specified by OrData, and writes the result to the 32-bit PCI\r
-  configuration register specified by Address. The value written to the PCI\r
-  configuration register is returned. This function must guarantee that all PCI\r
-  read and write operations are serialized.\r
-\r
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
+  followed a  bitwise inclusive OR with another 32-bit value.\r
+  \r
+  Reads the 32-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 32-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
-  @param  OrData  The value to OR with the result of the AND operation.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT32\r