Fix the unaligned issue of PCI read/write buffer.

[mirror_edk2.git] / MdePkg / Library / PeiPciSegmentLibPciCfg2 / PciSegmentLib.c

diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
index 6c327e2eb9164ff295888c9d7363cd0161e438f9..a08298aaa24f51f2ee687b11167bcd47e395d03a 100644 (file)
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI Segment Library implementation using PCI CFG2 PPI.\r
 \r
-  Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+  Copyright (c) 2007 - 2009, Intel Corporation All rights\r
   reserved. This program and the accompanying materials are\r
   licensed and made available under the terms and conditions of\r
   the BSD License which accompanies this distribution.  The full\r
@@ -25,14 +25,14 @@
 \r
 /**\r
   Assert the validity of a PCI Segment address.\r
-  A valid PCI Segment address should not contain 1's in bits 31:28\r
+  A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r
 \r
   @param  A The address to validate.\r
   @param  M Additional bits to assert to be zero.\r
 \r
 **/\r
 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
-  ASSERT (((A) & (0xf0000000 | (M))) == 0)\r
+  ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
 \r
 /**\r
   Translate PCI Lib address into format of PCI CFG2 PPI.\r
@@ -165,7 +165,7 @@ PeiPciSegmentLibPciCfg2WriteWorker (
   Register a PCI device so PCI configuration registers may be accessed after \r
   SetVirtualAddressMap().\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -185,6 +185,7 @@ PciSegmentRegisterForRuntimeAccess (
   IN UINTN  Address\r
   )\r
 {\r
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
   return RETURN_UNSUPPORTED;\r
 }\r
 \r
@@ -218,7 +219,7 @@ PciSegmentRead8 (
   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
   @param  Value       The value to write.\r
@@ -1208,7 +1209,7 @@ PciSegmentBitFieldAndThenOr32 (
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
@@ -1258,7 +1259,7 @@ PciSegmentReadBuffer (
     //\r
     // Read a word if StartAddress is word aligned\r
     //\r
-    *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r
+    WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
     StartAddress += sizeof (UINT16);\r
     Size -= sizeof (UINT16);\r
     Buffer = (UINT16*)Buffer + 1;\r
@@ -1268,7 +1269,7 @@ PciSegmentReadBuffer (
     //\r
     // Read as many double words as possible\r
     //\r
-    *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);\r
+    WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r
     StartAddress += sizeof (UINT32);\r
     Size -= sizeof (UINT32);\r
     Buffer = (UINT32*)Buffer + 1;\r
@@ -1278,7 +1279,7 @@ PciSegmentReadBuffer (
     //\r
     // Read the last remaining word if exist\r
     //\r
-    *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r
+    WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
     StartAddress += sizeof (UINT16);\r
     Size -= sizeof (UINT16);\r
     Buffer = (UINT16*)Buffer + 1;\r
@@ -1307,7 +1308,7 @@ PciSegmentReadBuffer (
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
@@ -1357,7 +1358,7 @@ PciSegmentWriteBuffer (
     //\r
     // Write a word if StartAddress is word aligned\r
     //\r
-    PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r
+    PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
     StartAddress += sizeof (UINT16);\r
     Size -= sizeof (UINT16);\r
     Buffer = (UINT16*)Buffer + 1;\r
@@ -1367,7 +1368,7 @@ PciSegmentWriteBuffer (
     //\r
     // Write as many double words as possible\r
     //\r
-    PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);\r
+    PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
     StartAddress += sizeof (UINT32);\r
     Size -= sizeof (UINT32);\r
     Buffer = (UINT32*)Buffer + 1;\r
@@ -1377,7 +1378,7 @@ PciSegmentWriteBuffer (
     //\r
     // Write the last remaining word if exist\r
     //\r
-    PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r
+    PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
     StartAddress += sizeof (UINT16);\r
     Size -= sizeof (UINT16);\r
     Buffer = (UINT16*)Buffer + 1;\r