## @libraryclass The multiple segments PCI configuration Library Services that carry out\r
## PCI configuration and enable the PCI operations to be replayed during an\r
## S3 resume. This library class maps directly on top of the PciSegmentLib class.\r
- S3PciSegmentLib|Include/Library/PciSegmentLib.h\r
+ S3PciSegmentLib|Include/Library/S3PciSegmentLib.h\r
\r
## @libraryclass Provides services to access PCI Configuration Space.\r
PciLib|Include/Library/PciLib.h\r
## Include/Guid/GraphicsInfoHob.h\r
gEfiGraphicsDeviceInfoHobGuid = { 0xe5cb2ac9, 0xd35d, 0x4430, { 0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7 }}\r
\r
+ ## Include/Guid/SmramMemoryReserve.h\r
+ gEfiSmmSmramMemoryGuid = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d }}\r
+\r
#\r
# GUID defined in PI1.6\r
#\r
## Include/Ppi/SecHobData.h\r
gEfiSecHobDataPpiGuid = { 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f } }\r
\r
+ ## Include/Ppi/MmAccess.h\r
+ gEfiPeiMmAccessPpiGuid = { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}\r
+\r
+ ## Include/Ppi/MmControl.h\r
+ gEfiPeiMmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }}\r
+\r
#\r
# PPIs defined in PI 1.7.\r
#\r