# It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of\r
# EFI1.10/UEFI2.7/PI1.7 and some Industry Standards.\r
#\r
-# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
+# (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP<BR>\r
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>\r
+# Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
\r
[Includes]\r
Include\r
+ Test/UnitTest/Include\r
\r
[Includes.IA32]\r
Include/Ia32\r
[Includes.AARCH64]\r
Include/AArch64\r
\r
+[Includes.RISCV64]\r
+ Include/RiscV64\r
+\r
+[Includes.LOONGARCH64]\r
+ Include/LoongArch64\r
+\r
[LibraryClasses]\r
## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec\r
# and the standard requests defined in Usb 1.1 spec.\r
#\r
UnitTestLib|Include/Library/UnitTestLib.h\r
\r
+ ## @libraryclass Extension to BaseLib for host based unit tests that allows a\r
+ # subset of BaseLib services to be hooked for emulation.\r
+ #\r
+ UnitTestHostBaseLib|Test/UnitTest/Include/Library/UnitTestHostBaseLib.h\r
+\r
+ ## @libraryclass This library provides an interface to request non-MMRAM pages to be mapped\r
+ # or unblocked from inside MM environment.\r
+ #\r
+ MmUnblockMemoryLib|Include/Library/MmUnblockMemoryLib.h\r
+\r
+ ## @libraryclass This library provides interfances to filter and trace port IO/MMIO/MSR access.\r
+ #\r
+ #\r
+ RegisterFilterLib|Include/Library/RegisterFilterLib.h\r
+\r
+ ## @libraryclass This library provides interfances to probe ConfidentialComputing guest type.\r
+ #\r
+ #\r
+ CcProbeLib|Include/Library/CcProbeLib.h\r
+\r
+ ## @libraryclass Provides function for SMM CPU Rendezvous Library.\r
+ SmmCpuRendezvousLib|Include/Library/SmmCpuRendezvousLib.h\r
+\r
+ ## @libraryclass Provides services to generate Entropy using a TRNG.\r
+ #\r
+ ArmTrngLib|Include/Library/ArmTrngLib.h\r
+\r
+[LibraryClasses.IA32, LibraryClasses.X64, LibraryClasses.AARCH64]\r
+ ## @libraryclass Provides services to generate random number.\r
+ #\r
+ RngLib|Include/Library/RngLib.h\r
+\r
[LibraryClasses.IA32, LibraryClasses.X64]\r
## @libraryclass Abstracts both S/W SMI generation and detection.\r
##\r
#\r
SmmPeriodicSmiLib|Include/Library/SmmPeriodicSmiLib.h\r
\r
- ## @libraryclass Provides services to generate random number.\r
- #\r
- RngLib|Include/Library/RngLib.h\r
-\r
## @libraryclass Provides services to log the SMI handler registration.\r
SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h\r
\r
+ ## @libraryclass Provides function to support TDX processing.\r
+ TdxLib|Include/Library/TdxLib.h\r
+\r
+[LibraryClasses.RISCV64]\r
+ ## @libraryclass Provides function to make ecalls to SBI\r
+ BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h\r
+\r
[Guids]\r
#\r
# GUID defined in UEFI2.1/UEFI2.0/EFI1.1\r
## Include/Guid/EventGroup.h\r
gEfiEventReadyToBootGuid = { 0x7CE88FB3, 0x4BD7, 0x4679, { 0x87, 0xA8, 0xA8, 0xD8, 0xDE, 0xE5, 0x0D, 0x2B }}\r
\r
+ ## Include/Guid/EventGroup.h\r
+ gEfiEventAfterReadyToBootGuid = { 0x3a2a00ad, 0x98b9, 0x4cdf, { 0xa4, 0x78, 0x70, 0x27, 0x77, 0xf1, 0xc1, 0x0b }}\r
+\r
## Include/Guid/EventGroup.h\r
gEfiEventMemoryMapChangeGuid = { 0x78BEE926, 0x692F, 0x48FD, { 0x9E, 0xDB, 0x01, 0x42, 0x2E, 0xF0, 0xD7, 0xAB }}\r
\r
## Include/Guid/EventGroup.h\r
- gEfiEventVirtualAddressChangeGuid = { 0x13FA7698, 0xC831, 0x49C7, { 0x87, 0xEA, 0x8F, 0x43, 0xFC, 0xC2, 0x51, 0x96 }}\r
+ gEfiEventVirtualAddressChangeGuid = { 0x13FA7698, 0xC831, 0x49C7, { 0x87, 0xEA, 0x8F, 0x43, 0xFC, 0xC2, 0x51, 0x96 }}\r
+\r
+ ## Include/Guid/EventGroup.h\r
+ gEfiEventBeforeExitBootServicesGuid = { 0x8BE0E274, 0x3970, 0x4B44, { 0x80, 0xC5, 0x1A, 0xB9, 0x50, 0x2F, 0x3B, 0xFC }}\r
\r
## Include/Guid/EventGroup.h\r
gEfiEventExitBootServicesGuid = { 0x27ABF055, 0xB1B8, 0x4C26, { 0x80, 0x48, 0x74, 0x8F, 0x37, 0xBA, 0xA2, 0xDF }}\r
## Include/Guid/Cper.h\r
gEfiEventNotificationTypeDmarGuid = { 0x667DD791, 0xC6B3, 0x4c27, { 0x8A, 0x6B, 0x0F, 0x8E, 0x72, 0x2D, 0xEB, 0x41 }}\r
\r
+ ## Include/Guid/Cper.h\r
+ gEfiEventNotificationTypeSeaGuid = { 0x9A78788A, 0xBBE8, 0x11E4, { 0x80, 0x9E, 0x67, 0x61, 0x1E, 0x5D, 0x46, 0xB0 }}\r
+\r
+ ## Include/Guid/Cper.h\r
+ gEfiEventNotificationTypeSeiGuid = { 0x5C284C81, 0xB0AE, 0x4E87, { 0xA3, 0x22, 0xB0, 0x4C, 0x85, 0x62, 0x43, 0x23 }}\r
+\r
+ ## Include/Guid/Cper.h\r
+ gEfiEventNotificationTypePeiGuid = { 0x09A9D5AC, 0x5204, 0x4214, { 0x96, 0xE5, 0x94, 0x99, 0x2E, 0x75, 0x2B, 0xCD }}\r
+\r
## Include/Guid/Cper.h\r
gEfiProcessorGenericErrorSectionGuid = { 0x9876ccad, 0x47b4, 0x4bdb, { 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb }}\r
\r
## Include/Guid/Btt.h\r
gEfiBttAbstractionGuid = { 0x18633bfc, 0x1735, 0x4217, { 0x8a, 0xc9, 0x17, 0x23, 0x92, 0x82, 0xd3, 0xf8 }}\r
\r
+ # GUIDs defined in UEFI2.8\r
+ #\r
+ ## Include/Guid/JsonCapsule.h\r
+ gEfiJsonConfigDataTableGuid = { 0x87367f87, 0x1119, 0x41ce, { 0xaa, 0xec, 0x8b, 0xe0, 0x11, 0x1f, 0x55, 0x8a }}\r
+ gEfiJsonCapsuleDataTableGuid = { 0x35e7a725, 0x8dd2, 0x4cac, { 0x80, 0x11, 0x33, 0xcd, 0xa8, 0x10, 0x90, 0x56 }}\r
+ gEfiJsonCapsuleResultTableGuid = { 0xdbc461c3, 0xb3de, 0x422a, { 0xb9, 0xb4, 0x98, 0x86, 0xfd, 0x49, 0xa1, 0xe5 }}\r
+ gEfiJsonCapsuleIdGuid = { 0x67d6f4cd, 0xd6b8, 0x4573, { 0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }}\r
+\r
+ ## Include/Guid/HiiPlatformSetupFormset.h\r
+ gEfiHiiRestStyleFormsetGuid = { 0x790217bd, 0xbecf, 0x485b, { 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 }}\r
+\r
+ # GUIDs defined in UEFI2.8a\r
+ #\r
+ ## Include/Guid/RtPropertiesTable.h\r
+ gEfiRtPropertiesTableGuid = { 0xeb66918a, 0x7eef, 0x402a, { 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }}\r
+\r
+ ## Include/Protocol/SerilaIo.h\r
+ gEfiSerialTerminalDeviceTypeGuid = { 0x6AD9A60F, 0x5815, 0x4C7C, { 0x8A, 0x10, 0x50, 0x53, 0xD2, 0xBF, 0x7A, 0x1B }}\r
+\r
#\r
# GUID defined in PI1.0\r
#\r
#\r
gTianoCustomDecompressGuid = { 0xA31280AD, 0x481E, 0x41B6, { 0x95, 0xE8, 0x12, 0x7F, 0x4C, 0x98, 0x47, 0x79 }}\r
\r
+ #\r
+ # GUID used to provide initrd to linux via LoadFile2 protocol\r
+ #\r
+ gLinuxEfiInitrdMediaGuid = {0x5568e427, 0x68fc, 0x4f3d, {0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68}}\r
+\r
+ ## Include/Protocol/CcMeasurement.h\r
+ gEfiCcFinalEventsTableGuid = { 0xdd4a4648, 0x2de7, 0x4665, { 0x96, 0x4d, 0x21, 0xd9, 0xef, 0x5f, 0xb4, 0x46 }}\r
+\r
[Guids.IA32, Guids.X64]\r
## Include/Guid/Cper.h\r
gEfiIa32X64ErrorTypeCacheCheckGuid = { 0xA55701F5, 0xE3EF, 0x43de, { 0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C }}\r
## Include/Ppi/MmControl.h\r
gEfiPeiMmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }}\r
\r
+ ## Include/Ppi/MmConfiguration.h\r
+ gEfiPeiMmConfigurationPpi = { 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } }\r
+\r
+ ## Include/Ppi/MmCommunication.h\r
+ gEfiPeiMmCommunicationPpiGuid = { 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } }\r
+\r
#\r
# PPIs defined in PI 1.7.\r
#\r
## Include/Ppi/PeiCoreFvLocation.h\r
gEfiPeiCoreFvLocationPpiGuid = { 0x52888eae, 0x5b10, 0x47d0, { 0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 }}\r
\r
+ ## Include/Ppi/DelayedDispatch.h\r
+ gEfiPeiDelayedDispatchPpiGuid = { 0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29, 0x11, 0xc3, 0xe6 }}\r
+\r
[Protocols]\r
+ ## Include/Protocol/MemoryAccept.h\r
+ gEdkiiMemoryAcceptProtocolGuid = { 0x38c74800, 0x5590, 0x4db4, { 0xa0, 0xf3, 0x67, 0x5d, 0x9b, 0x8e, 0x80, 0x26 }}\r
+\r
## Include/Protocol/Pcd.h\r
gPcdProtocolGuid = { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2, 0x90, 0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }}\r
\r
## Include/Protocol/PcdInfo.h\r
gGetPcdInfoProtocolGuid = { 0x5be40f57, 0xfa68, 0x4610, { 0xbb, 0xbf, 0xe9, 0xc5, 0xfc, 0xda, 0xd3, 0x65 } }\r
\r
+ ## Include/Protocol/CcMeasurement.h\r
+ gEfiCcMeasurementProtocolGuid = { 0x96751a3d, 0x72f4, 0x41a6, { 0xa7, 0x94, 0xed, 0x5d, 0x0e, 0x67, 0xae, 0x6b }}\r
+\r
#\r
# Protocols defined in PI1.0.\r
#\r
## Include/Protocol/SpiSmmNorFlash.h\r
gEfiSpiSmmNorFlashProtocolGuid = { 0xaab18f19, 0xfe14, 0x4666, { 0x86, 0x04, 0x87, 0xff, 0x6d, 0x66, 0x2c, 0x9a }}\r
\r
+ #\r
+ # Protocols defined in PI 1.7.\r
+ #\r
+\r
+ ## Include/Protocol/MmCommunication2.h\r
+ gEfiMmCommunication2ProtocolGuid = { 0x378daedc, 0xf06b, 0x4446, { 0x83, 0x14, 0x40, 0xab, 0x93, 0x3c, 0x87, 0xa3 }}\r
+\r
#\r
# Protocols defined in UEFI2.1/UEFI2.0/EFI1.1\r
#\r
## Include/Protocol/NvdimmLabel.h\r
gEfiNvdimmLabelProtocolGuid = { 0xd40b6b80, 0x97d5, 0x4282, { 0xbb, 0x1d, 0x22, 0x3a, 0x16, 0x91, 0x80, 0x58 }}\r
\r
+ #\r
+ # Protocols defined in UEFI2.8\r
+ #\r
+ ## Include/Protocol/RestEx.h\r
+ gEfiRestExProtocolGuid = { 0x55648b91, 0xe7d, 0x40a3, { 0xa9, 0xb3, 0xa8, 0x15, 0xd7, 0xea, 0xdf, 0x97 }}\r
+ gEfiRestExServiceBindingProtocolGuid = { 0x456bbe01, 0x99d0, 0x45ea, { 0xbb, 0x5f, 0x16, 0xd8, 0x4b, 0xed, 0xc5, 0x59 }}\r
+\r
+ ## Include/Protocol/RestJsonStructure.h\r
+ gEfiRestJsonStructureProtocolGuid = { 0xa9a048f6, 0x48a0, 0x4714, {0xb7, 0xda, 0xa9, 0xad,0x87, 0xd4, 0xda, 0xc9 }}\r
+\r
+ ## Include/Protocol/RedfishDiscover.h\r
+ gEfiRedfishDiscoverProtocolGuid = { 0x5db12509, 0x4550, 0x4347, { 0x96, 0xb3, 0x73, 0xc0, 0xff, 0x6e, 0x86, 0x9f }}\r
+\r
#\r
# Protocols defined in Shell2.0\r
#\r
# @ValidList 0x80000001 | 8, 16, 32\r
gEfiMdePkgTokenSpaceGuid.PcdPort80DataWidth|8|UINT8|0x0000002d\r
\r
- ## This value is used to configure X86 Processor FSB clock.\r
- # @Prompt FSB Clock.\r
- gEfiMdePkgTokenSpaceGuid.PcdFSBClock|200000000|UINT32|0x0000000c\r
-\r
## The maximum printable number of characters. UefLib functions: AsciiPrint(), AsciiErrorPrint(),\r
# PrintXY(), AsciiPrintXY(), Print(), ErrorPrint() base on this PCD value to print characters.\r
# @Prompt Maximum Printable Number of Characters.\r
# @Prompt PCI Express Base Address.\r
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x0000000a\r
\r
+ ## This value is used to set the base address of PCI MMIO window that provides I/O access.\r
+ # @Prompt PCI I/O Memory Map Window Base Address.\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000040\r
+\r
+ ## This value is used for the 32-bit PCI memory map I/O base address translation.\r
+ # @Prompt 32-bit PCI Memory Map I/O Base Address translation.\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000041\r
+\r
+ ## This value is used for the 64-bit PCI memory map I/O base address translation.\r
+ # @Prompt 64-bit PCI Memory Map I/O Base Address translation.\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000042\r
+\r
+ ## This value is used to set the size of PCI express hierarchy. The default is 256 MB.\r
+ # @Prompt PCI Express Base Size.\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000|UINT64|0x0000000f\r
+\r
## Default current ISO 639-2 language: English & French.\r
# @Prompt Default Value of LangCodes Variable.\r
gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001c\r
# @Prompt Boot Timeout (s)\r
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000002c\r
\r
+ ## This value is used to configure X86 Processor FSB clock.\r
+ # @Prompt FSB Clock.\r
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|200000000|UINT32|0x0000000c\r
+\r
+ ## This dynamic PCD indicates the memory encryption attribute of the guest.\r
+ # @Prompt Memory encryption attribute\r
+ gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0|UINT64|0x0000002e\r
+\r
[UserExtensions.TianoCore."ExtraFiles"]\r
MdePkgExtra.uni\r