#define WSPR (0x048)
-#define TISR_TCAR_IT_FLAG_MASK (1UL << 2)
-#define TISR_OVF_IT_FLAG_MASK (1UL << 1)
-#define TISR_MAT_IT_FLAG_MASK (1UL << 0)
+#define TISR_TCAR_IT_FLAG_MASK BIT2
+#define TISR_OVF_IT_FLAG_MASK BIT1
+#define TISR_MAT_IT_FLAG_MASK BIT0
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
-#define TISR_TCAR_IT_FLAG_CLEAR (1UL << 2)
-#define TISR_OVF_IT_FLAG_CLEAR (1UL << 1)
-#define TISR_MAT_IT_FLAG_CLEAR (1UL << 0)
+#define TISR_TCAR_IT_FLAG_CLEAR BIT2
+#define TISR_OVF_IT_FLAG_CLEAR BIT1
+#define TISR_MAT_IT_FLAG_CLEAR BIT0
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
-#define TCLR_AR_AUTORELOAD (1UL << 1)
+#define TCLR_AR_AUTORELOAD BIT1
#define TCLR_AR_ONESHOT (0UL << 1)
-#define TCLR_ST_ON (1UL << 0)
+#define TCLR_ST_ON BIT0
#define TCLR_ST_OFF (0UL << 0)
-#define TIER_TCAR_IT_ENABLE (1UL << 2)
+#define TIER_TCAR_IT_ENABLE (BIT2
#define TIER_TCAR_IT_DISABLE (0UL << 2)
-#define TIER_OVF_IT_ENABLE (1UL << 1)
+#define TIER_OVF_IT_ENABLE BIT1
#define TIER_OVF_IT_DISABLE (0UL << 1)
-#define TIER_MAT_IT_ENABLE (1UL << 0)
+#define TIER_MAT_IT_ENABLE BIT0
#define TIER_MAT_IT_DISABLE (0UL << 0)
#endif // __OMAP3530TIMER_H__