//\r
// System Sleep States\r
//\r
+ // We build S3 and S4 with GetSuspendStates() in\r
+ // "OvmfPkg/AcpiPlatformDxe/Qemu.c".\r
+ //\r
Name (\_S0, Package () {5, 0, 0, 0}) // Working\r
- Name (\_S4, Package () {1, 0, 0, 0}) // Suspend to Disk\r
Name (\_S5, Package () {0, 0, 0, 0}) // Soft Off\r
\r
//\r
)\r
})\r
\r
- Method (_CRS, 0) {\r
+ Method (_CRS, 0, Serialized) {\r
//\r
// see the FIRMWARE_DATA structure in "OvmfPkg/AcpiPlatformDxe/Qemu.c"\r
//\r
Package () {0x0000FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r
Package () {0x0000FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r
\r
- Package () {0x0001FFFF, 0x00, 0x00, 0x09},\r
//\r
- // list of IRQs occupied thus far: 9\r
+ // Bus 0, Device 1, Pin 0 (INTA) is special; it corresponds to the\r
+ // internally generated SCI (System Control Interrupt), which is\r
+ // always routed to GSI 9. By setting the third (= Source) field to\r
+ // zero, we could use the fourth (= Source Index) field to hardwire\r
+ // the pin to GSI 9 directly.\r
+ //\r
+ // That way however, in accordance with the ACPI spec's description\r
+ // of SCI, the interrupt would be treated as "active low,\r
+ // shareable, level", and that doesn't match qemu.\r
//\r
+ // In QemuInstallAcpiMadtTable() [OvmfPkg/AcpiPlatformDxe/Qemu.c]\r
+ // we install an Interrupt Override Structure for the identity\r
+ // mapped IRQ#9 / GSI 9 (the corresponding bit being set in\r
+ // Pcd8259LegacyModeEdgeLevel), which describes the correct\r
+ // polarity (active high). As a consequence, some OS'en (eg. Linux)\r
+ // override the default (active low) polarity originating from the\r
+ // _PRT; others (eg. FreeBSD) don't. Therefore we need a separate\r
+ // link device just to specify a polarity that matches the MADT.\r
+ //\r
+ Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKS, 0x00},\r
+\r
Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
Device (LPC) {\r
Name (_ADR, 0x00010000)\r
\r
+ //\r
+ // The SCI cannot be rerouted or disabled with PIRQRC[A:D]; we only\r
+ // need this link device in order to specify the polarity.\r
+ //\r
+ Device (LNKS) {\r
+ Name (_HID, EISAID("PNP0C0F"))\r
+ Name (_UID, 0)\r
+\r
+ Name (_STA, 0xB) // 0x1: device present\r
+ // 0x2: enabled and decoding resources\r
+ // 0x8: functioning properly\r
+\r
+ Method (_SRS, 1, NotSerialized) { /* no-op */ }\r
+ Method (_DIS, 0, NotSerialized) { /* no-op */ }\r
+\r
+ Name (_PRS, ResourceTemplate () {\r
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { 9 }\r
+ //\r
+ // list of IRQs occupied thus far: 9\r
+ //\r
+ })\r
+ Method (_CRS, 0, NotSerialized) { Return (_PRS) }\r
+ }\r
+\r
//\r
// PCI Interrupt Routing Configuration Registers, PIRQRC[A:D]\r
//\r
// _CRS method for LNKA, LNKB, LNKC, LNKD\r
// Arg0[in]: value of PIRA / PIRB / PIRC / PIRD\r
//\r
- Method (PCRS, 1, NotSerialized) {\r
+ Method (PCRS, 1, Serialized) {\r
//\r
// create temporary buffer with an Extended Interrupt Descriptor\r
// whose single vector defaults to zero\r
IO (Decode16, 0x278, 0x278, 0x00, 0x08)\r
IO (Decode16, 0x370, 0x370, 0x00, 0x02)\r
IO (Decode16, 0x378, 0x378, 0x00, 0x08)\r
- IO (Decode16, 0x402, 0x402, 0x00, 0x01) // QEMU debug console, should use FixedPcdGet16 (PcdDebugIoPort)\r
+ IO (Decode16, FixedPcdGet16 (PcdDebugIoPort), FixedPcdGet16 (PcdDebugIoPort), 0x00, 0x01)\r
IO (Decode16, 0x440, 0x440, 0x00, 0x10)\r
IO (Decode16, 0x678, 0x678, 0x00, 0x08)\r
IO (Decode16, 0x778, 0x778, 0x00, 0x08)\r