\r
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
\r
- This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
// 0xEC000-0xEFFFF 0x5f 0x96 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
// 0xF0000-0xFFFFF 0x59 0x90 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
//\r
-STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = {\r
- {0xC0000, SIZE_16KB, FALSE, FALSE},\r
- {0xC4000, SIZE_16KB, FALSE, FALSE},\r
- {0xC8000, SIZE_16KB, FALSE, FALSE},\r
- {0xCC000, SIZE_16KB, FALSE, FALSE},\r
- {0xD0000, SIZE_16KB, FALSE, FALSE},\r
- {0xD4000, SIZE_16KB, FALSE, FALSE},\r
- {0xD8000, SIZE_16KB, FALSE, FALSE},\r
- {0xDC000, SIZE_16KB, FALSE, FALSE},\r
- {0xE0000, SIZE_16KB, FALSE, FALSE},\r
- {0xE4000, SIZE_16KB, FALSE, FALSE},\r
- {0xE8000, SIZE_16KB, FALSE, FALSE},\r
- {0xEC000, SIZE_16KB, FALSE, FALSE},\r
- {0xF0000, SIZE_64KB, FALSE, FALSE}\r
+STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = {\r
+ { 0xC0000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xC4000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xC8000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xCC000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xD0000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xD4000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xD8000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xDC000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xE0000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xE4000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xE8000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xEC000, SIZE_16KB, FALSE, FALSE },\r
+ { 0xF0000, SIZE_64KB, FALSE, FALSE }\r
};\r
\r
STATIC PAM_REGISTER_VALUE mRegisterValues440[] = {\r
- {REG_PAM1_OFFSET_440, 0x01, 0x02},\r
- {REG_PAM1_OFFSET_440, 0x10, 0x20},\r
- {REG_PAM2_OFFSET_440, 0x01, 0x02},\r
- {REG_PAM2_OFFSET_440, 0x10, 0x20},\r
- {REG_PAM3_OFFSET_440, 0x01, 0x02},\r
- {REG_PAM3_OFFSET_440, 0x10, 0x20},\r
- {REG_PAM4_OFFSET_440, 0x01, 0x02},\r
- {REG_PAM4_OFFSET_440, 0x10, 0x20},\r
- {REG_PAM5_OFFSET_440, 0x01, 0x02},\r
- {REG_PAM5_OFFSET_440, 0x10, 0x20},\r
- {REG_PAM6_OFFSET_440, 0x01, 0x02},\r
- {REG_PAM6_OFFSET_440, 0x10, 0x20},\r
- {REG_PAM0_OFFSET_440, 0x10, 0x20}\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x01, 0x02 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x10, 0x20 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x01, 0x02 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x10, 0x20 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x01, 0x02 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x10, 0x20 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x01, 0x02 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x10, 0x20 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x01, 0x02 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x10, 0x20 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x01, 0x02 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x10, 0x20 },\r
+ { PMC_REGISTER_PIIX4 (PIIX4_PAM0), 0x10, 0x20 }\r
};\r
\r
STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] = {\r
- {REG_PAM1_OFFSET_Q35, 0x01, 0x02},\r
- {REG_PAM1_OFFSET_Q35, 0x10, 0x20},\r
- {REG_PAM2_OFFSET_Q35, 0x01, 0x02},\r
- {REG_PAM2_OFFSET_Q35, 0x10, 0x20},\r
- {REG_PAM3_OFFSET_Q35, 0x01, 0x02},\r
- {REG_PAM3_OFFSET_Q35, 0x10, 0x20},\r
- {REG_PAM4_OFFSET_Q35, 0x01, 0x02},\r
- {REG_PAM4_OFFSET_Q35, 0x10, 0x20},\r
- {REG_PAM5_OFFSET_Q35, 0x01, 0x02},\r
- {REG_PAM5_OFFSET_Q35, 0x10, 0x20},\r
- {REG_PAM6_OFFSET_Q35, 0x01, 0x02},\r
- {REG_PAM6_OFFSET_Q35, 0x10, 0x20},\r
- {REG_PAM0_OFFSET_Q35, 0x10, 0x20}\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM1), 0x01, 0x02 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM1), 0x10, 0x20 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM2), 0x01, 0x02 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM2), 0x10, 0x20 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM3), 0x01, 0x02 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM3), 0x10, 0x20 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM4), 0x01, 0x02 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM4), 0x10, 0x20 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM5), 0x01, 0x02 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM5), 0x10, 0x20 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM6), 0x01, 0x02 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM6), 0x10, 0x20 },\r
+ { DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20 }\r
};\r
\r
-STATIC PAM_REGISTER_VALUE *mRegisterValues;\r
+STATIC PAM_REGISTER_VALUE *mRegisterValues;\r
\r
//\r
// Handle used to install the Legacy Region Protocol\r
STATIC\r
EFI_STATUS\r
LegacyRegionManipulationInternal (\r
- IN UINT32 Start,\r
- IN UINT32 Length,\r
- IN BOOLEAN *ReadEnable,\r
- IN BOOLEAN *WriteEnable,\r
- OUT UINT32 *Granularity\r
+ IN UINT32 Start,\r
+ IN UINT32 Length,\r
+ IN BOOLEAN *ReadEnable,\r
+ IN BOOLEAN *WriteEnable,\r
+ OUT UINT32 *Granularity\r
)\r
{\r
- UINT32 EndAddress;\r
- UINTN Index;\r
- UINTN StartIndex;\r
+ UINT32 EndAddress;\r
+ UINTN Index;\r
+ UINTN StartIndex;\r
\r
//\r
// Validate input parameters.\r
//\r
- if (Length == 0 || Granularity == NULL) {\r
+ if ((Length == 0) || (Granularity == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
EndAddress = Start + Length - 1;\r
- if ((Start < PAM_BASE_ADDRESS) || EndAddress > PAM_LIMIT_ADDRESS) {\r
+ if ((Start < PAM_BASE_ADDRESS) || (EndAddress > PAM_LIMIT_ADDRESS)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
break;\r
}\r
}\r
+\r
ASSERT (Index < ARRAY_SIZE (mSectionArray));\r
\r
//\r
if (ReadEnable != NULL) {\r
if (*ReadEnable) {\r
PciOr8 (\r
- PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
+ mRegisterValues[Index].PAMRegPciLibAddress,\r
mRegisterValues[Index].ReadEnableData\r
);\r
} else {\r
PciAnd8 (\r
- PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
- (UINT8) (~mRegisterValues[Index].ReadEnableData)\r
+ mRegisterValues[Index].PAMRegPciLibAddress,\r
+ (UINT8)(~mRegisterValues[Index].ReadEnableData)\r
);\r
}\r
}\r
+\r
if (WriteEnable != NULL) {\r
if (*WriteEnable) {\r
PciOr8 (\r
- PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
+ mRegisterValues[Index].PAMRegPciLibAddress,\r
mRegisterValues[Index].WriteEnableData\r
);\r
} else {\r
PciAnd8 (\r
- PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
- (UINT8) (~mRegisterValues[Index].WriteEnableData)\r
+ mRegisterValues[Index].PAMRegPciLibAddress,\r
+ (UINT8)(~mRegisterValues[Index].WriteEnableData)\r
);\r
}\r
}\r
break;\r
}\r
}\r
+\r
ASSERT (Index < ARRAY_SIZE (mSectionArray));\r
\r
return EFI_SUCCESS;\r
STATIC\r
EFI_STATUS\r
LegacyRegionGetInfoInternal (\r
- OUT UINT32 *DescriptorCount,\r
- OUT LEGACY_MEMORY_SECTION_INFO **Descriptor\r
+ OUT UINT32 *DescriptorCount,\r
+ OUT LEGACY_MEMORY_SECTION_INFO **Descriptor\r
)\r
{\r
- UINTN Index;\r
- UINT8 PamValue;\r
+ UINTN Index;\r
+ UINT8 PamValue;\r
\r
//\r
// Check input parameters\r
//\r
- if (DescriptorCount == NULL || Descriptor == NULL) {\r
+ if ((DescriptorCount == NULL) || (Descriptor == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
// Fill in current status of legacy region.\r
//\r
- *DescriptorCount = sizeof(mSectionArray) / sizeof (mSectionArray[0]);\r
+ *DescriptorCount = sizeof (mSectionArray) / sizeof (mSectionArray[0]);\r
for (Index = 0; Index < *DescriptorCount; Index++) {\r
- PamValue = PciRead8 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset));\r
+ PamValue = PciRead8 (mRegisterValues[Index].PAMRegPciLibAddress);\r
mSectionArray[Index].ReadEnabled = FALSE;\r
if ((PamValue & mRegisterValues[Index].ReadEnableData) != 0) {\r
mSectionArray[Index].ReadEnabled = TRUE;\r
}\r
+\r
mSectionArray[Index].WriteEnabled = FALSE;\r
if ((PamValue & mRegisterValues[Index].WriteEnableData) != 0) {\r
mSectionArray[Index].WriteEnabled = TRUE;\r
return LegacyRegionManipulationInternal (Start, Length, On, NULL, Granularity);\r
}\r
\r
-\r
/**\r
Modify the hardware to disallow memory attribute changes in a region.\r
\r
EFI_STATUS\r
EFIAPI\r
LegacyRegion2BootLock (\r
- IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
- IN UINT32 Start,\r
- IN UINT32 Length,\r
- OUT UINT32 *Granularity\r
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
+ IN UINT32 Start,\r
+ IN UINT32 Length,\r
+ OUT UINT32 *Granularity\r
)\r
{\r
if ((Start < 0xC0000) || ((Start + Length - 1) > 0xFFFFF)) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
-\r
/**\r
Modify the hardware to disallow memory writes in a region.\r
\r
EFI_STATUS\r
EFIAPI\r
LegacyRegion2Lock (\r
- IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
- IN UINT32 Start,\r
- IN UINT32 Length,\r
- OUT UINT32 *Granularity\r
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
+ IN UINT32 Start,\r
+ IN UINT32 Length,\r
+ OUT UINT32 *Granularity\r
)\r
{\r
BOOLEAN WriteEnable;\r
return LegacyRegionManipulationInternal (Start, Length, NULL, &WriteEnable, Granularity);\r
}\r
\r
-\r
/**\r
Modify the hardware to allow memory writes in a region.\r
\r
OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor\r
)\r
{\r
- LEGACY_MEMORY_SECTION_INFO *SectionInfo;\r
- UINT32 SectionCount;\r
- EFI_LEGACY_REGION_DESCRIPTOR *DescriptorArray;\r
- UINTN Index;\r
- UINTN DescriptorIndex;\r
+ LEGACY_MEMORY_SECTION_INFO *SectionInfo;\r
+ UINT32 SectionCount;\r
+ EFI_LEGACY_REGION_DESCRIPTOR *DescriptorArray;\r
+ UINTN Index;\r
+ UINTN DescriptorIndex;\r
\r
//\r
// Get section numbers and information\r
DescriptorArray[DescriptorIndex].Length = SectionInfo[Index].Length;\r
DescriptorArray[DescriptorIndex].Granularity = SectionInfo[Index].Length;\r
if (SectionInfo[Index].ReadEnabled) {\r
- DescriptorArray[DescriptorIndex].Attribute = LegacyRegionDecoded;\r
+ DescriptorArray[DescriptorIndex].Attribute = LegacyRegionDecoded;\r
} else {\r
- DescriptorArray[DescriptorIndex].Attribute = LegacyRegionNotDecoded;\r
+ DescriptorArray[DescriptorIndex].Attribute = LegacyRegionNotDecoded;\r
}\r
+\r
DescriptorIndex++;\r
\r
//\r
} else {\r
DescriptorArray[DescriptorIndex].Attribute = LegacyRegionWriteDisabled;\r
}\r
+\r
DescriptorIndex++;\r
\r
//\r
DescriptorIndex++;\r
}\r
\r
- *DescriptorCount = (UINT32) DescriptorIndex;\r
+ *DescriptorCount = (UINT32)DescriptorIndex;\r
*Descriptor = DescriptorArray;\r
\r
return EFI_SUCCESS;\r
//\r
HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
switch (HostBridgeDevId) {\r
- case INTEL_82441_DEVICE_ID:\r
- mRegisterValues = mRegisterValues440;\r
- break;\r
- case INTEL_Q35_MCH_DEVICE_ID:\r
- mRegisterValues = mRegisterValuesQ35;\r
- break;\r
- default:\r
- DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
- __FUNCTION__, HostBridgeDevId));\r
- ASSERT (FALSE);\r
- return RETURN_UNSUPPORTED;\r
+ case INTEL_82441_DEVICE_ID:\r
+ mRegisterValues = mRegisterValues440;\r
+ break;\r
+ case INTEL_Q35_MCH_DEVICE_ID:\r
+ mRegisterValues = mRegisterValuesQ35;\r
+ break;\r
+ default:\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ __FUNCTION__,\r
+ HostBridgeDevId\r
+ ));\r
+ ASSERT (FALSE);\r
+ return RETURN_UNSUPPORTED;\r
}\r
\r
//\r
//\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&mHandle,\r
- &gEfiLegacyRegion2ProtocolGuid, &mLegacyRegion2,\r
+ &gEfiLegacyRegion2ProtocolGuid,\r
+ &mLegacyRegion2,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Status;\r
}\r
-\r