UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()

[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / Q35MchIch9.h

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 4f59a7c0e3e0f52eedc67fb2b509bb65d3e101f0..193a262e5b543d1cfed4a78942e2257e30eb3ec7 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -19,6 +19,9 @@
 #define __Q35_MCH_ICH9_H__\r
 \r
 #include <Library/PciLib.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Uefi/UefiSpec.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
 \r
 //\r
 // Host Bridge Device ID (DID) value for Q35/MCH\r
@@ -30,9 +33,28 @@
 //\r
 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
 \r
+#define MCH_EXT_TSEG_MB       0x50\r
+#define MCH_EXT_TSEG_MB_QUERY   0xFFFF\r
+\r
 #define MCH_GGC               0x52\r
 #define MCH_GGC_IVD             BIT1\r
 \r
+#define MCH_PCIEXBAR_LOW      0x60\r
+#define MCH_PCIEXBAR_LOWMASK    0x0FFFFFFF\r
+#define MCH_PCIEXBAR_BUS_FF     0\r
+#define MCH_PCIEXBAR_EN         BIT0\r
+\r
+#define MCH_PCIEXBAR_HIGH     0x64\r
+#define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0\r
+\r
+#define MCH_PAM0              0x90\r
+#define MCH_PAM1              0x91\r
+#define MCH_PAM2              0x92\r
+#define MCH_PAM3              0x93\r
+#define MCH_PAM4              0x94\r
+#define MCH_PAM5              0x95\r
+#define MCH_PAM6              0x96\r
+\r
 #define MCH_SMRAM             0x9D\r
 #define MCH_SMRAM_D_LCK         BIT4\r
 #define MCH_SMRAM_G_SMRAME      BIT3\r
@@ -43,6 +65,7 @@
 #define MCH_ESMRAMC_SM_CACHE    BIT5\r
 #define MCH_ESMRAMC_SM_L1       BIT4\r
 #define MCH_ESMRAMC_SM_L2       BIT3\r
+#define MCH_ESMRAMC_TSEG_EXT    (BIT2 | BIT1)\r
 #define MCH_ESMRAMC_TSEG_8MB    BIT2\r
 #define MCH_ESMRAMC_TSEG_2MB    BIT1\r
 #define MCH_ESMRAMC_TSEG_1MB    0\r
@@ -67,6 +90,9 @@
 #define POWER_MGMT_REGISTER_Q35(Offset) \\r
   PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))\r
 \r
+#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \\r
+  EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))\r
+\r
 #define ICH9_PMBASE               0x40\r
 #define ICH9_PMBASE_MASK            (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r
                                      BIT10 | BIT9  | BIT8  | BIT7)\r
@@ -77,6 +103,9 @@
 #define ICH9_GEN_PMCON_1          0xA0\r
 #define ICH9_GEN_PMCON_1_SMI_LOCK   BIT4\r
 \r
+#define ICH9_RCBA                 0xF0\r
+#define ICH9_RCBA_EN                BIT0\r
+\r
 //\r
 // IO ports\r
 //\r
@@ -90,4 +119,6 @@
 #define ICH9_SMI_EN_APMC_EN      BIT5\r
 #define ICH9_SMI_EN_GBL_SMI_EN   BIT0\r
 \r
+#define ICH9_ROOT_COMPLEX_BASE 0xFED1C000\r
+\r
 #endif\r