UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()

[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / Q35MchIch9.h

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index f480455ae4326ba583ff29052ba79e275651a75f..193a262e5b543d1cfed4a78942e2257e30eb3ec7 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -33,6 +33,9 @@
 //\r
 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
 \r
+#define MCH_EXT_TSEG_MB       0x50\r
+#define MCH_EXT_TSEG_MB_QUERY   0xFFFF\r
+\r
 #define MCH_GGC               0x52\r
 #define MCH_GGC_IVD             BIT1\r
 \r
@@ -44,6 +47,14 @@
 #define MCH_PCIEXBAR_HIGH     0x64\r
 #define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0\r
 \r
+#define MCH_PAM0              0x90\r
+#define MCH_PAM1              0x91\r
+#define MCH_PAM2              0x92\r
+#define MCH_PAM3              0x93\r
+#define MCH_PAM4              0x94\r
+#define MCH_PAM5              0x95\r
+#define MCH_PAM6              0x96\r
+\r
 #define MCH_SMRAM             0x9D\r
 #define MCH_SMRAM_D_LCK         BIT4\r
 #define MCH_SMRAM_G_SMRAME      BIT3\r
@@ -54,6 +65,7 @@
 #define MCH_ESMRAMC_SM_CACHE    BIT5\r
 #define MCH_ESMRAMC_SM_L1       BIT4\r
 #define MCH_ESMRAMC_SM_L2       BIT3\r
+#define MCH_ESMRAMC_TSEG_EXT    (BIT2 | BIT1)\r
 #define MCH_ESMRAMC_TSEG_8MB    BIT2\r
 #define MCH_ESMRAMC_TSEG_2MB    BIT1\r
 #define MCH_ESMRAMC_TSEG_1MB    0\r