OvmfPkg/CpuHotplugSmm: introduce skeleton for CPU Hotplug SMM driver

[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / Q35MchIch9.h

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 391cb4622226beaa32efb4c2f562963720d62990..73db4b59a1112840b0fdf9d3210412fe869d19db 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -27,56 +27,62 @@
 //\r
 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
 \r
-#define MCH_EXT_TSEG_MB       0x50\r
-#define MCH_EXT_TSEG_MB_QUERY   0xFFFF\r
-\r
-#define MCH_GGC               0x52\r
-#define MCH_GGC_IVD             BIT1\r
-\r
-#define MCH_PCIEXBAR_LOW      0x60\r
-#define MCH_PCIEXBAR_LOWMASK    0x0FFFFFFF\r
-#define MCH_PCIEXBAR_BUS_FF     0\r
-#define MCH_PCIEXBAR_EN         BIT0\r
-\r
-#define MCH_PCIEXBAR_HIGH     0x64\r
-#define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0\r
-\r
-#define MCH_PAM0              0x90\r
-#define MCH_PAM1              0x91\r
-#define MCH_PAM2              0x92\r
-#define MCH_PAM3              0x93\r
-#define MCH_PAM4              0x94\r
-#define MCH_PAM5              0x95\r
-#define MCH_PAM6              0x96\r
-\r
-#define MCH_SMRAM             0x9D\r
-#define MCH_SMRAM_D_LCK         BIT4\r
-#define MCH_SMRAM_G_SMRAME      BIT3\r
-\r
-#define MCH_ESMRAMC           0x9E\r
-#define MCH_ESMRAMC_H_SMRAME    BIT7\r
-#define MCH_ESMRAMC_E_SMERR     BIT6\r
-#define MCH_ESMRAMC_SM_CACHE    BIT5\r
-#define MCH_ESMRAMC_SM_L1       BIT4\r
-#define MCH_ESMRAMC_SM_L2       BIT3\r
-#define MCH_ESMRAMC_TSEG_EXT    (BIT2 | BIT1)\r
-#define MCH_ESMRAMC_TSEG_8MB    BIT2\r
-#define MCH_ESMRAMC_TSEG_2MB    BIT1\r
-#define MCH_ESMRAMC_TSEG_1MB    0\r
-#define MCH_ESMRAMC_TSEG_MASK   (BIT2 | BIT1)\r
-#define MCH_ESMRAMC_T_EN        BIT0\r
-\r
-#define MCH_GBSM              0xA4\r
-#define MCH_GBSM_MB_SHIFT       20\r
-\r
-#define MCH_BGSM              0xA8\r
-#define MCH_BGSM_MB_SHIFT       20\r
-\r
-#define MCH_TSEGMB            0xAC\r
-#define MCH_TSEGMB_MB_SHIFT     20\r
-\r
-#define MCH_TOLUD             0xB0\r
-#define MCH_TOLUD_MB_SHIFT      4\r
+#define MCH_EXT_TSEG_MB           0x50\r
+#define MCH_EXT_TSEG_MB_QUERY       0xFFFF\r
+\r
+#define MCH_GGC                   0x52\r
+#define MCH_GGC_IVD                 BIT1\r
+\r
+#define MCH_PCIEXBAR_LOW          0x60\r
+#define MCH_PCIEXBAR_LOWMASK        0x0FFFFFFF\r
+#define MCH_PCIEXBAR_BUS_FF         0\r
+#define MCH_PCIEXBAR_EN             BIT0\r
+\r
+#define MCH_PCIEXBAR_HIGH         0x64\r
+#define MCH_PCIEXBAR_HIGHMASK       0xFFFFFFF0\r
+\r
+#define MCH_PAM0                  0x90\r
+#define MCH_PAM1                  0x91\r
+#define MCH_PAM2                  0x92\r
+#define MCH_PAM3                  0x93\r
+#define MCH_PAM4                  0x94\r
+#define MCH_PAM5                  0x95\r
+#define MCH_PAM6                  0x96\r
+\r
+#define MCH_DEFAULT_SMBASE_CTL    0x9C\r
+#define MCH_DEFAULT_SMBASE_QUERY    0xFF\r
+#define MCH_DEFAULT_SMBASE_IN_RAM   0x01\r
+#define MCH_DEFAULT_SMBASE_LCK      0x02\r
+#define MCH_DEFAULT_SMBASE_SIZE     SIZE_128KB\r
+\r
+#define MCH_SMRAM                 0x9D\r
+#define MCH_SMRAM_D_LCK             BIT4\r
+#define MCH_SMRAM_G_SMRAME          BIT3\r
+\r
+#define MCH_ESMRAMC               0x9E\r
+#define MCH_ESMRAMC_H_SMRAME        BIT7\r
+#define MCH_ESMRAMC_E_SMERR         BIT6\r
+#define MCH_ESMRAMC_SM_CACHE        BIT5\r
+#define MCH_ESMRAMC_SM_L1           BIT4\r
+#define MCH_ESMRAMC_SM_L2           BIT3\r
+#define MCH_ESMRAMC_TSEG_EXT        (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_TSEG_8MB        BIT2\r
+#define MCH_ESMRAMC_TSEG_2MB        BIT1\r
+#define MCH_ESMRAMC_TSEG_1MB        0\r
+#define MCH_ESMRAMC_TSEG_MASK       (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_T_EN            BIT0\r
+\r
+#define MCH_GBSM                  0xA4\r
+#define MCH_GBSM_MB_SHIFT           20\r
+\r
+#define MCH_BGSM                  0xA8\r
+#define MCH_BGSM_MB_SHIFT           20\r
+\r
+#define MCH_TSEGMB                0xAC\r
+#define MCH_TSEGMB_MB_SHIFT         20\r
+\r
+#define MCH_TOLUD                 0xB0\r
+#define MCH_TOLUD_MB_SHIFT          4\r
 \r
 //\r
 // B/D/F/Type: 0/0x1f/0/PCI\r
@@ -103,8 +109,11 @@
 //\r
 // IO ports\r
 //\r
-#define ICH9_APM_CNT 0xB2\r
-#define ICH9_APM_STS 0xB3\r
+#define ICH9_APM_CNT              0xB2\r
+#define ICH9_APM_CNT_CPU_HOTPLUG    0x04\r
+#define ICH9_APM_STS              0xB3\r
+\r
+#define ICH9_CPU_HOTPLUG_BASE 0x0CD8\r
 \r
 //\r
 // IO ports relative to PMBASE\r