\r
Copyright (C) 2014, Gabriel L. Somlo <somlo@cmu.edu>\r
\r
- This program and the accompanying materials are licensed and made\r
- available under the terms and conditions of the BSD License which\r
- accompanies this distribution. The full text of the license may\r
- be found at http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
-#include <Library/PcdLib.h>\r
#include <OvmfPlatforms.h>\r
\r
//\r
{\r
UINT16 HostBridgeDevId;\r
UINTN Pmba;\r
+ UINT32 PmbaAndVal;\r
+ UINT32 PmbaOrVal;\r
UINTN AcpiCtlReg;\r
UINT8 AcpiEnBit;\r
\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
+ PmbaOrVal = PIIX4_PMBA_VALUE;\r
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
+ PmbaOrVal = ICH9_PMBASE_VALUE;\r
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
//\r
// If the Power Management Base Address is not programmed,\r
- // then program the Power Management Base Address from a PCD.\r
+ // then program it now.\r
//\r
- PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+ PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
\r
//\r
// Enable PMBA I/O port decodes\r