OvmfPkg/PlatformBootManagerLib: connect Virtio RNG devices again

[mirror_edk2.git] / OvmfPkg / Library / AcpiTimerLib / BaseRomAcpiTimerLib.c

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index 05b14d724668e617d8a70834459577c556175c16..dbbecc93c116dd3d47badb060dd5013e59c961f5 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -16,20 +16,8 @@
 #include <Library/DebugLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/PciLib.h>\r
-#include <Library/PcdLib.h>\r
 #include <OvmfPlatforms.h>\r
 \r
-//\r
-// Power Management PCI Configuration Register fields\r
-//\r
-#define PMBA_RTE  BIT0\r
-#define PMIOSE    BIT0\r
-\r
-//\r
-// Offset in the Power Management Base Address to the ACPI Timer\r
-//\r
-#define ACPI_TIMER_OFFSET      0x8\r
-\r
 /**\r
   The constructor function enables ACPI IO space.\r
 \r
@@ -47,7 +35,10 @@ AcpiTimerLibConstructor (
 {\r
   UINT16 HostBridgeDevId;\r
   UINTN Pmba;\r
-  UINTN PmRegMisc;\r
+  UINT32 PmbaAndVal;\r
+  UINT32 PmbaOrVal;\r
+  UINTN AcpiCtlReg;\r
+  UINT8 AcpiEnBit;\r
 \r
   //\r
   // Query Host Bridge DID to determine platform type\r
@@ -55,12 +46,18 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
+      PmbaOrVal  = PIIX4_PMBA_VALUE;\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_Q35 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
+      PmbaOrVal  = ICH9_PMBASE_VALUE;\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
@@ -72,17 +69,17 @@ AcpiTimerLibConstructor (
   //\r
   // Check to see if the Power Management Base Address is already enabled\r
   //\r
-  if ((PciRead8 (PmRegMisc) & PMIOSE) == 0) {\r
+  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
     //\r
     // If the Power Management Base Address is not programmed,\r
-    // then program the Power Management Base Address from a PCD.\r
+    // then program it now.\r
     //\r
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
 \r
     //\r
-    // Enable PMBA I/O port decodes in PMREGMISC\r
+    // Enable PMBA I/O port decodes\r
     //\r
-    PciOr8 (PmRegMisc, PMIOSE);\r
+    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
 \r
   return RETURN_SUCCESS;\r
@@ -111,10 +108,10 @@ InternalAcpiGetTimerTick (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
-      Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
+      Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r