OvmfPkg/QemuFwCfgDxeLib: SEV: zero FW_CFG_DMA_ACCESS before decrypting it

[mirror_edk2.git] / OvmfPkg / Library / AcpiTimerLib / DxeAcpiTimerLib.c

diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
index 649b5c9a4d72ff972abb318a6113095668290ae9..e673434ae66baf807bfa8aad665aa33c7f25c8e7 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
@@ -18,16 +18,6 @@
 #include <Library/PciLib.h>\r
 #include <OvmfPlatforms.h>\r
 \r
-//\r
-// Power Management PCI Configuration Register fields\r
-//\r
-#define PMBA_RTE  BIT0\r
-\r
-//\r
-// Offset in the Power Management Base Address to the ACPI Timer\r
-//\r
-#define ACPI_TIMER_OFFSET  0x8\r
-\r
 //\r
 // Cached ACPI Timer IO Address\r
 //\r
@@ -61,7 +51,7 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r