FIRMWARE_CONFIG_ITEM FwCfgItem;\r
UINTN FwCfgSize;\r
UINT64 HotPlugMemoryEnd;\r
+ RETURN_STATUS PcdStatus;\r
\r
FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",\r
__FUNCTION__));\r
- PcdSet64 (PcdPciMmio64Size, 0);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
//\r
// the GCD memory space map through our PciHostBridgeLib instance; here we\r
// only need to set the PCDs.\r
//\r
- PcdSet64 (PcdPciMmio64Base, Pci64Base);\r
- PcdSet64 (PcdPciMmio64Size, Pci64Size);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
__FUNCTION__, Pci64Base, Pci64Size));\r
}\r
EFI_STATUS Status;\r
EFI_PHYSICAL_ADDRESS MemoryBase;\r
UINT64 MemorySize;\r
- UINT64 LowerMemorySize;\r
+ UINT32 LowerMemorySize;\r
UINT32 PeiMemoryCap;\r
\r
LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
//\r
if (mS3Supported) {\r
mS3AcpiReservedMemorySize = SIZE_512KB +\r
- PcdGet32 (PcdCpuMaxLogicalProcessorNumber) *\r
+ mMaxCpuCount *\r
PcdGet32 (PcdCpuApStackSize);\r
mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r
LowerMemorySize = mS3AcpiReservedMemoryBase;\r
// PEI RAM, in a backup buffer allocated with the normal PEI services.\r
// CpuMpPei restores the original contents ("returns" the borrowed area) at\r
// End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r
- // transfering control to the OS's wakeup vector in the FACS.\r
+ // transferring control to the OS's wakeup vector in the FACS.\r
//\r
// We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r
// restore the original contents. Furthermore, we expect all such PEIMs\r