};\r
\r
\r
+UINT16 mHostBridgeDevId;\r
+\r
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
\r
BOOLEAN mS3Supported = FALSE;\r
// 0xFEC00000 IO-APIC 4 KB\r
// 0xFEC01000 gap 1020 KB\r
// 0xFED00000 HPET 1 KB\r
- // 0xFED00400 gap 1023 KB\r
+ // 0xFED00400 gap 111 KB\r
+ // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
+ // 0xFED20000 gap 896 KB\r
// 0xFEE00000 LAPIC 1 MB\r
//\r
AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
BASE_2GB : TopOfLowRam, 0xFC000000);\r
AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+ }\r
AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
}\r
}\r
VOID\r
)\r
{\r
- UINT16 HostBridgeDevId;\r
UINTN PmCmd;\r
UINTN Pmba;\r
- UINTN PmRegMisc;\r
+ UINTN AcpiCtlReg;\r
+ UINT8 AcpiEnBit;\r
\r
//\r
// Disable A20 Mask\r
IoOr8 (0x92, BIT1);\r
\r
//\r
- // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+ // S3 resume as well, so we build it unconditionally.)\r
//\r
- BuildCpuHob (36, 16);\r
+ BuildCpuHob (mPhysMemAddressWidth, 16);\r
\r
//\r
- // Query Host Bridge DID to determine platform type\r
+ // Determine platform type and save Host Bridge DID to PCD\r
//\r
- HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
- switch (HostBridgeDevId) {\r
+ switch (mHostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
- PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+ PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
- PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+ PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
- __FUNCTION__, HostBridgeDevId));\r
+ __FUNCTION__, mHostBridgeDevId));\r
ASSERT (FALSE);\r
return;\r
}\r
+ PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
\r
//\r
- // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
- // example by Xen) and skip the setup here. This matches the logic in\r
- // AcpiTimerLibConstructor ().\r
+ // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
+ // has been configured (e.g., by Xen) and skip the setup here.\r
+ // This matches the logic in AcpiTimerLibConstructor ().\r
//\r
- if ((PciRead8 (PmRegMisc) & 0x01) == 0) {\r
+ if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
//\r
- // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+ // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
// 1. set PMBA\r
//\r
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
\r
//\r
- // 3. set PMREGMISC/PMIOSE\r
+ // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
//\r
- PciOr8 (PmRegMisc, 0x01);\r
+ PciOr8 (AcpiCtlReg, AcpiEnBit);\r
+ }\r
+\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ //\r
+ // Set Root Complex Register Block BAR\r
+ //\r
+ PciWrite32 (\r
+ POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
+ ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
+ );\r
}\r
}\r
\r
if (CmosRead8 (0xF) == 0xFE) {\r
mBootMode = BOOT_ON_S3_RESUME;\r
}\r
+ CmosWrite8 (0xF, 0x00);\r
\r
Status = PeiServicesSetBootMode (mBootMode);\r
ASSERT_EFI_ERROR (Status);\r
VOID\r
)\r
{\r
- UINTN Loop;\r
+ UINT32 Loop;\r
\r
DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
}\r
\r
BootModeInitialization ();\r
+ AddressWidthInitialization ();\r
\r
PublishPeiMemory ();\r
\r
InitializeXen ();\r
}\r
\r
+ //\r
+ // Query Host Bridge DID\r
+ //\r
+ mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
ReserveEmuVariableNvStore ();\r
\r