Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
+#include <Library/QemuFwCfgS3Lib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
\r
BOOLEAN mS3Supported = FALSE;\r
\r
+UINT32 mMaxCpuCount;\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
VOID\r
)\r
{\r
- UINT64 PciIoBase;\r
- UINT64 PciIoSize;\r
+ UINT64 PciIoBase;\r
+ UINT64 PciIoSize;\r
+ RETURN_STATUS PcdStatus;\r
\r
PciIoBase = 0xC000;\r
PciIoSize = 0x4000;\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
} else {\r
- PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+ ASSERT (TopOfLowRam <= mQemuUc32Base);\r
+ PciBase = mQemuUc32Base;\r
}\r
\r
//\r
//\r
PciSize = 0xFC000000 - PciBase;\r
AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
- PcdSet64 (PcdPciMmio32Base, PciBase);\r
- PcdSet64 (PcdPciMmio32Size, PciSize);\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
EfiReservedMemoryType);\r
}\r
AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+\r
+ //\r
+ // On Q35, the IO Port space is available for PCI resource allocations from\r
+ // 0x6000 up.\r
+ //\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ PciIoBase = 0x6000;\r
+ PciIoSize = 0xA000;\r
+ ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
+ }\r
}\r
\r
//\r
PciIoBase,\r
PciIoSize\r
);\r
- PcdSet64 (PcdPciIoBase, PciIoBase);\r
- PcdSet64 (PcdPciIoSize, PciIoSize);\r
+ PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
EFI_STATUS\r
\r
#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
do { \\r
- BOOLEAN Setting; \\r
+ BOOLEAN Setting; \\r
+ RETURN_STATUS PcdStatus; \\r
\\r
if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
"opt/ovmf/" #TokenName, &Setting))) { \\r
- PcdSetBool (TokenName, Setting); \\r
+ PcdStatus = PcdSetBoolS (TokenName, Setting); \\r
+ ASSERT_RETURN_ERROR (PcdStatus); \\r
} \\r
} while (0)\r
\r
VOID\r
)\r
{\r
- UINTN PmCmd;\r
- UINTN Pmba;\r
- UINT32 PmbaAndVal;\r
- UINT32 PmbaOrVal;\r
- UINTN AcpiCtlReg;\r
- UINT8 AcpiEnBit;\r
+ UINTN PmCmd;\r
+ UINTN Pmba;\r
+ UINT32 PmbaAndVal;\r
+ UINT32 PmbaOrVal;\r
+ UINTN AcpiCtlReg;\r
+ UINT8 AcpiEnBit;\r
+ RETURN_STATUS PcdStatus;\r
\r
//\r
// Disable A20 Mask\r
ASSERT (FALSE);\r
return;\r
}\r
- PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
\r
//\r
// If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
)\r
{\r
EFI_PHYSICAL_ADDRESS VariableStore;\r
+ RETURN_STATUS PcdStatus;\r
\r
//\r
// Allocate storage for NV variables early on so it will be\r
//\r
VariableStore =\r
(EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateAlignedRuntimePages (\r
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
- PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+ AllocateRuntimePages (\r
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
);\r
DEBUG ((EFI_D_INFO,\r
"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
VariableStore,\r
(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
));\r
- PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
+ PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
\r
}\r
\r
\r
+/**\r
+ Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r
+ Set the mMaxCpuCount variable.\r
+**/\r
+VOID\r
+MaxCpuCountInitialization (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 ProcessorCount;\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
+ ProcessorCount = QemuFwCfgRead16 ();\r
+ //\r
+ // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r
+ // from the PCD default. No change to PCDs.\r
+ //\r
+ if (ProcessorCount == 0) {\r
+ mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+ return;\r
+ }\r
+ //\r
+ // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r
+ //\r
+ mMaxCpuCount = ProcessorCount;\r
+ //\r
+ // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r
+ // to wait, in the initial AP bringup, exactly as long as it takes for all of\r
+ // the APs to report in. For this, we set the longest representable timeout\r
+ // (approx. 71 minutes).\r
+ //\r
+ PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r
+ ProcessorCount));\r
+}\r
+\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
{\r
EFI_STATUS Status;\r
\r
- DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
+ DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
\r
S3Verification ();\r
BootModeInitialization ();\r
AddressWidthInitialization ();\r
+ MaxCpuCountInitialization ();\r
+\r
+ //\r
+ // Query Host Bridge DID\r
+ //\r
+ mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+\r
+ if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ Q35TsegMbytesInitialization ();\r
+ }\r
\r
PublishPeiMemory ();\r
\r
+ QemuUc32BaseInitialization ();\r
+\r
InitializeRamRegions ();\r
\r
if (mXen) {\r
InitializeXen ();\r
}\r
\r
- //\r
- // Query Host Bridge DID\r
- //\r
- mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
-\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
- ReserveEmuVariableNvStore ();\r
+ if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ ReserveEmuVariableNvStore ();\r
+ }\r
PeiFvInitialization ();\r
MemMapInitialization ();\r
NoexecDxeInitialization ();\r
}\r
\r
+ InstallClearCacheCallback ();\r
+ AmdSevInitialize ();\r
MiscInitialization ();\r
+ InstallFeatureControlCallback ();\r
\r
return EFI_SUCCESS;\r
}\r