OvmfPkg: Add NullMemoryTestDxe driver

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index d35a1fbb5c0115e8df198330799693136f187574..66bb0984c864e8c44538496367d9a05214d8625d 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -31,11 +31,12 @@
 #include <Guid/MemoryTypeInformation.h>\r
 \r
 #include "Platform.h"\r
+#include "Cmos.h"\r
 \r
 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
   { EfiACPIMemoryNVS,       0x004 },\r
   { EfiACPIReclaimMemory,   0x008 },\r
-  { EfiReservedMemoryType,  0x004 },     \r
+  { EfiReservedMemoryType,  0x004 },\r
   { EfiRuntimeServicesData, 0x024 },\r
   { EfiRuntimeServicesCode, 0x030 },\r
   { EfiBootServicesCode,    0x180 },\r
@@ -104,6 +105,7 @@ AddMemoryRangeHob (
 \r
 VOID\r
 MemMapInitialization (\r
+  EFI_PHYSICAL_ADDRESS  TopOfMemory\r
   )\r
 {\r
   //\r
@@ -129,22 +131,26 @@ MemMapInitialization (
   //\r
   // Add PCI MMIO space available to PCI resource allocations\r
   //\r
-  AddIoMemoryBaseSizeHob (0x80000000, 0xFEC00000 - 0x80000000);\r
+  if (TopOfMemory < BASE_2GB) {\r
+    AddIoMemoryBaseSizeHob (BASE_2GB, 0xFEC00000 - BASE_2GB);\r
+  } else {\r
+    AddIoMemoryBaseSizeHob (TopOfMemory, 0xFEC00000 - TopOfMemory);\r
+  }\r
 \r
   //\r
   // Local APIC range\r
   //\r
-  AddIoMemoryBaseSizeHob (0xFEC80000, 0x80000);\r
+  AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
 \r
   //\r
   // I/O APIC range\r
   //\r
-  AddIoMemoryBaseSizeHob (0xFEC00000, 0x80000);\r
+  AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
 \r
   //\r
   // Video memory + Legacy BIOS region\r
   //\r
-  AddIoMemoryRangeHob (0x0A0000, 0x100000);\r
+  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
 }\r
 \r
 \r
@@ -155,12 +161,17 @@ MiscInitialization (
   //\r
   // Disable A20 Mask\r
   //\r
-  IoWrite8 (0x92, (UINT8) (IoRead8 (0x92) | 0x02));\r
+  IoOr8 (0x92, BIT1);\r
 \r
   //\r
   // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
   //\r
   BuildCpuHob (36, 16);\r
+\r
+  //\r
+  // Set the PM I/O base address to 0x400\r
+  //\r
+  PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
 }\r
 \r
 \r
@@ -190,6 +201,27 @@ ReserveEmuVariableNvStore (
 }\r
 \r
 \r
+VOID\r
+DebugDumpCmos (\r
+  VOID\r
+  )\r
+{\r
+  UINTN  Loop;\r
+\r
+  DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
+\r
+  for (Loop = 0; Loop < 0x80; Loop++) {\r
+    if ((Loop % 0x10) == 0) {\r
+      DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
+    }\r
+    DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
+    if ((Loop % 0x10) == 0xf) {\r
+      DEBUG ((EFI_D_INFO, "\n"));\r
+    }\r
+  }\r
+}\r
+\r
+\r
 /**\r
   Perform Platform PEI initialization.\r
 \r
@@ -206,15 +238,19 @@ InitializePlatform (
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r
+  EFI_PHYSICAL_ADDRESS  TopOfMemory;\r
+\r
   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
 \r
-  MemDetect ();\r
+  DebugDumpCmos ();\r
+\r
+  TopOfMemory = MemDetect ();\r
 \r
   ReserveEmuVariableNvStore ();\r
 \r
   PeiFvInitialization ();\r
 \r
-  MemMapInitialization ();\r
+  MemMapInitialization (TopOfMemory);\r
 \r
   MiscInitialization ();\r
 \r