//\r
// The Library classes this module consumes\r
//\r
+#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
+#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
};\r
\r
\r
+UINT16 mHostBridgeDevId;\r
+\r
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+BOOLEAN mS3Supported = FALSE;\r
+\r
+\r
VOID\r
AddIoMemoryBaseSizeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
+ UINT64 MemorySize,\r
+ BOOLEAN Cacheable\r
)\r
{\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ (Cacheable ?\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
+ 0\r
+ ) |\r
EFI_RESOURCE_ATTRIBUTE_TESTED,\r
MemoryBase,\r
MemorySize\r
}\r
\r
VOID\r
-XenMemMapInitialization (\r
+MemMapInitialization (\r
VOID\r
)\r
{\r
//\r
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
- XenPublishRamRegions ();\r
-}\r
+ if (!mXen) {\r
+ UINT32 TopOfLowRam;\r
+ UINT32 PciBase;\r
+\r
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ //\r
+ // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
+ // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
+ // the RAM below 4 GB exceed it.\r
+ //\r
+ PciBase = BASE_2GB + BASE_1GB;\r
+ ASSERT (TopOfLowRam <= PciBase);\r
+ } else {\r
+ PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+ }\r
\r
+ //\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 111 KB\r
+ // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
+ // 0xFED20000 gap 896 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
+ //\r
+ AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+ }\r
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+ }\r
+}\r
\r
-VOID\r
-MemMapInitialization (\r
- EFI_PHYSICAL_ADDRESS TopOfMemory\r
+EFI_STATUS\r
+GetNamedFwCfgBoolean (\r
+ IN CHAR8 *FwCfgFileName,\r
+ OUT BOOLEAN *Setting\r
)\r
{\r
- //\r
- // Create Memory Type Information HOB\r
- //\r
- BuildGuidDataHob (\r
- &gEfiMemoryTypeInformationGuid,\r
- mDefaultMemoryTypeInformation,\r
- sizeof(mDefaultMemoryTypeInformation)\r
- );\r
-\r
- //\r
- // Add PCI IO Port space available for PCI resource allocations.\r
- //\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- 0xC000,\r
- 0x4000\r
- );\r
+ EFI_STATUS Status;\r
+ FIRMWARE_CONFIG_ITEM FwCfgItem;\r
+ UINTN FwCfgSize;\r
+ UINT8 Value[3];\r
+\r
+ Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if (FwCfgSize > sizeof Value) {\r
+ return EFI_BAD_BUFFER_SIZE;\r
+ }\r
+ QemuFwCfgSelectItem (FwCfgItem);\r
+ QemuFwCfgReadBytes (FwCfgSize, Value);\r
+\r
+ if ((FwCfgSize == 1) ||\r
+ (FwCfgSize == 2 && Value[1] == '\n') ||\r
+ (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
+ switch (Value[0]) {\r
+ case '0':\r
+ case 'n':\r
+ case 'N':\r
+ *Setting = FALSE;\r
+ return EFI_SUCCESS;\r
+\r
+ case '1':\r
+ case 'y':\r
+ case 'Y':\r
+ *Setting = TRUE;\r
+ return EFI_SUCCESS;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ return EFI_PROTOCOL_ERROR;\r
+}\r
\r
- //\r
- // Video memory + Legacy BIOS region\r
- //\r
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
+ do { \\r
+ BOOLEAN Setting; \\r
+ \\r
+ if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
+ "opt/ovmf/" #TokenName, &Setting))) { \\r
+ PcdSetBool (TokenName, Setting); \\r
+ } \\r
+ } while (0)\r
\r
- //\r
- // address purpose size\r
- // ------------ -------- -------------------------\r
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
- // 0xFC000000 gap 44 MB\r
- // 0xFEC00000 IO-APIC 4 KB\r
- // 0xFEC01000 gap 1020 KB\r
- // 0xFED00000 HPET 1 KB\r
- // 0xFED00400 gap 1023 KB\r
- // 0xFEE00000 LAPIC 1 MB\r
- //\r
- AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+VOID\r
+NoexecDxeInitialization (\r
+ VOID\r
+ )\r
+{\r
+ UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
+ UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
}\r
\r
-\r
VOID\r
MiscInitialization (\r
VOID\r
)\r
{\r
+ UINTN PmCmd;\r
+ UINTN Pmba;\r
+ UINTN AcpiCtlReg;\r
+ UINT8 AcpiEnBit;\r
+\r
//\r
// Disable A20 Mask\r
//\r
IoOr8 (0x92, BIT1);\r
\r
//\r
- // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+ // S3 resume as well, so we build it unconditionally.)\r
//\r
- BuildCpuHob (36, 16);\r
+ BuildCpuHob (mPhysMemAddressWidth, 16);\r
\r
//\r
- // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
- // example by Xen) and skip the setup here. This matches the logic in\r
- // AcpiTimerLibConstructor ().\r
+ // Determine platform type and save Host Bridge DID to PCD\r
//\r
- if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
+ switch (mHostBridgeDevId) {\r
+ case INTEL_82441_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
+ break;\r
+ case INTEL_Q35_MCH_DEVICE_ID:\r
+ PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
+ break;\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ __FUNCTION__, mHostBridgeDevId));\r
+ ASSERT (FALSE);\r
+ return;\r
+ }\r
+ PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+\r
+ //\r
+ // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
+ // has been configured (e.g., by Xen) and skip the setup here.\r
+ // This matches the logic in AcpiTimerLibConstructor ().\r
+ //\r
+ if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
//\r
- // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+ // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
// 1. set PMBA\r
//\r
- PciAndThenOr32 (\r
- PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
- (UINT32) ~0xFFC0,\r
- PcdGet16 (PcdAcpiPmBaseAddress)\r
- );\r
+ PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
\r
//\r
// 2. set PCICMD/IOSE\r
//\r
- PciOr8 (\r
- PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
- EFI_PCI_COMMAND_IO_SPACE\r
- );\r
+ PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
\r
//\r
- // 3. set PMREGMISC/PMIOSE\r
+ // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
//\r
- PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
+ PciOr8 (AcpiCtlReg, AcpiEnBit);\r
+ }\r
+\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ //\r
+ // Set Root Complex Register Block BAR\r
+ //\r
+ PciWrite32 (\r
+ POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
+ ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
+ );\r
}\r
}\r
\r
\r
VOID\r
BootModeInitialization (\r
+ VOID\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
+\r
+ if (CmosRead8 (0xF) == 0xFE) {\r
+ mBootMode = BOOT_ON_S3_RESUME;\r
+ }\r
+ CmosWrite8 (0xF, 0x00);\r
\r
- Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
+ Status = PeiServicesSetBootMode (mBootMode);\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = PeiServicesInstallPpi (mPpiBootMode);\r
VOID\r
)\r
{\r
- UINTN Loop;\r
+ UINT32 Loop;\r
\r
DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
}\r
\r
\r
+VOID\r
+S3Verification (\r
+ VOID\r
+ )\r
+{\r
+#if defined (MDE_CPU_X64)\r
+ if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
+ DEBUG ((EFI_D_ERROR,\r
+ "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
+ DEBUG ((EFI_D_ERROR,\r
+ "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
+ __FUNCTION__));\r
+ DEBUG ((EFI_D_ERROR,\r
+ "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
+ }\r
+#endif\r
+}\r
+\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS TopOfMemory;\r
-\r
- TopOfMemory = 0;\r
-\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
\r
XenDetect ();\r
\r
+ if (QemuFwCfgS3Enabled ()) {\r
+ DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
+ mS3Supported = TRUE;\r
+ }\r
+\r
+ S3Verification ();\r
BootModeInitialization ();\r
+ AddressWidthInitialization ();\r
\r
PublishPeiMemory ();\r
\r
- if (mXen) {\r
- PcdSetBool (PcdPciDisableBusEnumeration, TRUE);\r
- } else {\r
- TopOfMemory = MemDetect ();\r
- }\r
+ InitializeRamRegions ();\r
\r
if (mXen) {\r
DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
InitializeXen ();\r
}\r
\r
- ReserveEmuVariableNvStore ();\r
-\r
- PeiFvInitialization ();\r
+ //\r
+ // Query Host Bridge DID\r
+ //\r
+ mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
- if (mXen) {\r
- XenMemMapInitialization ();\r
- } else {\r
- MemMapInitialization (TopOfMemory);\r
+ if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ ReserveEmuVariableNvStore ();\r
+ PeiFvInitialization ();\r
+ MemMapInitialization ();\r
+ NoexecDxeInitialization ();\r
}\r
\r
MiscInitialization ();\r