);\r
\r
//\r
- // Add PCI MMIO space available to PCI resource allocations\r
- //\r
- if (TopOfMemory < BASE_2GB) {\r
- AddIoMemoryBaseSizeHob (BASE_2GB, 0xFC000000 - BASE_2GB);\r
- } else {\r
- AddIoMemoryBaseSizeHob (TopOfMemory, 0xFC000000 - TopOfMemory);\r
- }\r
-\r
- //\r
- // Local APIC range\r
- //\r
- AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
-\r
- //\r
- // I/O APIC range\r
+ // Video memory + Legacy BIOS region\r
//\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
+ AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
//\r
- // Video memory + Legacy BIOS region\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFEC00000 - max(top, 2g)\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 1023 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
//\r
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+ AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFEC00000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
}\r
\r
\r