/**@file\r
Platform PEI driver\r
\r
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
This program and the accompanying materials\r
}\r
\r
\r
-VOID\r
-AddUntestedMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-\r
-VOID\r
-AddUntestedMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
VOID\r
MemMapInitialization (\r
VOID\r
)\r
{\r
+ UINT64 PciIoBase;\r
+ UINT64 PciIoSize;\r
+\r
+ PciIoBase = 0xC000;\r
+ PciIoSize = 0x4000;\r
+\r
//\r
// Create Memory Type Information HOB\r
//\r
sizeof(mDefaultMemoryTypeInformation)\r
);\r
\r
- //\r
- // Add PCI IO Port space available for PCI resource allocations.\r
- //\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- 0xC000,\r
- 0x4000\r
- );\r
-\r
//\r
// Video memory + Legacy BIOS region\r
//\r
\r
if (!mXen) {\r
UINT32 TopOfLowRam;\r
+ UINT64 PciExBarBase;\r
UINT32 PciBase;\r
+ UINT32 PciSize;\r
\r
TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+ PciExBarBase = 0;\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
- // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
- // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
- // the RAM below 4 GB exceed it.\r
+ // The MMCONFIG area is expected to fall between the top of low RAM and\r
+ // the base of the 32-bit PCI host aperture.\r
//\r
- PciBase = BASE_2GB + BASE_1GB;\r
- ASSERT (TopOfLowRam <= PciBase);\r
+ PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+ ASSERT (TopOfLowRam <= PciExBarBase);\r
+ ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
+ PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
} else {\r
PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
}\r
// 0xFED20000 gap 896 KB\r
// 0xFEE00000 LAPIC 1 MB\r
//\r
- AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
+ PciSize = 0xFC000000 - PciBase;\r
+ AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
+ PcdSet64 (PcdPciMmio32Base, PciBase);\r
+ PcdSet64 (PcdPciMmio32Size, PciSize);\r
AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+ //\r
+ // Note: there should be an\r
+ //\r
+ // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
+ //\r
+ // call below, just like the one above for RCBA. However, Linux insists\r
+ // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
+ // "reserved memory" -- Linux does not content itself with a simple gap\r
+ // in the memory map wherever the MCFG ACPI table points to.\r
+ //\r
+ // This appears to be a safety measure. The PCI Firmware Specification\r
+ // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
+ // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
+ // [...]". (Emphasis added here.)\r
+ //\r
+ // Normally we add memory resource descriptor HOBs in\r
+ // QemuInitializeRam(), and pre-allocate from those with memory\r
+ // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
+ // is most definitely not RAM; so, as an exception, cover it with\r
+ // uncacheable reserved memory right here.\r
+ //\r
+ AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
+ BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r
+ EfiReservedMemoryType);\r
}\r
AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+\r
+ //\r
+ // On Q35, the IO Port space is available for PCI resource allocations from\r
+ // 0x6000 up.\r
+ //\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ PciIoBase = 0x6000;\r
+ PciIoSize = 0xA000;\r
+ ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
+ }\r
}\r
+\r
+ //\r
+ // Add PCI IO Port space available for PCI resource allocations.\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_IO,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+ PciIoBase,\r
+ PciIoSize\r
+ );\r
+ PcdSet64 (PcdPciIoBase, PciIoBase);\r
+ PcdSet64 (PcdPciIoSize, PciIoSize);\r
}\r
\r
EFI_STATUS\r
UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
}\r
\r
+VOID\r
+PciExBarInitialization (\r
+ VOID\r
+ )\r
+{\r
+ union {\r
+ UINT64 Uint64;\r
+ UINT32 Uint32[2];\r
+ } PciExBarBase;\r
+\r
+ //\r
+ // We only support the 256MB size for the MMCONFIG area:\r
+ // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
+ //\r
+ // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
+ // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
+ //\r
+ // Note that (b) also ensures that the minimum address width we have\r
+ // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
+ // for DXE's page tables to cover the MMCONFIG area.\r
+ //\r
+ PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+ ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
+ ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
+\r
+ //\r
+ // Clear the PCIEXBAREN bit first, before programming the high register.\r
+ //\r
+ PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
+\r
+ //\r
+ // Program the high register. Then program the low register, setting the\r
+ // MMCONFIG area size and enabling decoding at once.\r
+ //\r
+ PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
+ PciWrite32 (\r
+ DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
+ PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
+ );\r
+}\r
+\r
VOID\r
MiscInitialization (\r
VOID\r
{\r
UINTN PmCmd;\r
UINTN Pmba;\r
+ UINT32 PmbaAndVal;\r
+ UINT32 PmbaOrVal;\r
UINTN AcpiCtlReg;\r
UINT8 AcpiEnBit;\r
\r
case INTEL_82441_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
+ PmbaOrVal = PIIX4_PMBA_VALUE;\r
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
+ PmbaOrVal = ICH9_PMBASE_VALUE;\r
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
// The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
// 1. set PMBA\r
//\r
- PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+ PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
\r
//\r
// 2. set PCICMD/IOSE\r
POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
);\r
+\r
+ //\r
+ // Set PCI Express Register Range Base Address\r
+ //\r
+ PciExBarInitialization ();\r
}\r
}\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
+ EFI_STATUS Status;\r
+\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
if (QemuFwCfgS3Enabled ()) {\r
DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
mS3Supported = TRUE;\r
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
\r
S3Verification ();\r