/**@file\r
Platform PEI driver\r
\r
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
This program and the accompanying materials\r
}\r
\r
\r
-VOID\r
-AddUntestedMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-\r
-VOID\r
-AddUntestedMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
VOID\r
MemMapInitialization (\r
VOID\r
)\r
{\r
+ UINT64 PciIoBase;\r
+ UINT64 PciIoSize;\r
+\r
+ PciIoBase = 0xC000;\r
+ PciIoSize = 0x4000;\r
+\r
//\r
// Create Memory Type Information HOB\r
//\r
sizeof(mDefaultMemoryTypeInformation)\r
);\r
\r
- //\r
- // Add PCI IO Port space available for PCI resource allocations.\r
- //\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- PcdGet64 (PcdPciIoBase),\r
- PcdGet64 (PcdPciIoSize)\r
- );\r
-\r
//\r
// Video memory + Legacy BIOS region\r
//\r
UINT32 PciSize;\r
\r
TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+ PciExBarBase = 0;\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// The MMCONFIG area is expected to fall between the top of low RAM and\r
EfiReservedMemoryType);\r
}\r
AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+\r
+ //\r
+ // On Q35, the IO Port space is available for PCI resource allocations from\r
+ // 0x6000 up.\r
+ //\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ PciIoBase = 0x6000;\r
+ PciIoSize = 0xA000;\r
+ ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
+ }\r
}\r
+\r
+ //\r
+ // Add PCI IO Port space available for PCI resource allocations.\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_IO,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+ PciIoBase,\r
+ PciIoSize\r
+ );\r
+ PcdSet64 (PcdPciIoBase, PciIoBase);\r
+ PcdSet64 (PcdPciIoSize, PciIoSize);\r
}\r
\r
EFI_STATUS\r
{\r
UINTN PmCmd;\r
UINTN Pmba;\r
+ UINT32 PmbaAndVal;\r
+ UINT32 PmbaOrVal;\r
UINTN AcpiCtlReg;\r
UINT8 AcpiEnBit;\r
\r
case INTEL_82441_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
+ PmbaOrVal = PIIX4_PMBA_VALUE;\r
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
+ PmbaOrVal = ICH9_PMBASE_VALUE;\r
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
// The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
// 1. set PMBA\r
//\r
- PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+ PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
\r
//\r
// 2. set PCICMD/IOSE\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
+ EFI_STATUS Status;\r
+\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
if (QemuFwCfgS3Enabled ()) {\r
DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
mS3Supported = TRUE;\r
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
\r
S3Verification ();\r