/**@file\r
Platform PEI driver\r
\r
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
//\r
// The Library classes this module consumes\r
//\r
+#include <Library/BaseMemoryLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
+#include <Library/QemuFwCfgS3Lib.h>\r
+#include <Library/QemuFwCfgSimpleParserLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
-#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/I440FxPiix4.h>\r
+#include <IndustryStandard/Microvm.h>\r
#include <IndustryStandard/Pci22.h>\r
+#include <IndustryStandard/Q35MchIch9.h>\r
+#include <IndustryStandard/QemuCpuHotplug.h>\r
+#include <Library/MemEncryptSevLib.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
-#include "Cmos.h"\r
-\r
-EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
- { EfiACPIMemoryNVS, 0x004 },\r
- { EfiACPIReclaimMemory, 0x008 },\r
- { EfiReservedMemoryType, 0x004 },\r
- { EfiRuntimeServicesData, 0x024 },\r
- { EfiRuntimeServicesCode, 0x030 },\r
- { EfiBootServicesCode, 0x180 },\r
- { EfiBootServicesData, 0xF00 },\r
- { EfiMaxMemoryType, 0x000 }\r
-};\r
\r
+EFI_HOB_PLATFORM_INFO mPlatformInfoHob = { 0 };\r
\r
-EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
{\r
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
&gEfiPeiMasterBootModePpiGuid,\r
}\r
};\r
\r
-\r
-UINT16 mHostBridgeDevId;\r
-\r
-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
-\r
-BOOLEAN mS3Supported = FALSE;\r
-\r
-\r
VOID\r
-AddIoMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
+MemMapInitialization (\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_MEMORY_MAPPED_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
+ RETURN_STATUS PcdStatus;\r
\r
-VOID\r
-AddReservedMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize,\r
- BOOLEAN Cacheable\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_MEMORY_RESERVED,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- (Cacheable ?\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
- 0\r
- ) |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
+ PlatformMemMapInitialization (PlatformInfoHob);\r
\r
-VOID\r
-AddIoMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
+ if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {\r
+ return;\r
+ }\r
\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Base, PlatformInfoHob->PcdPciMmio32Base);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Size, PlatformInfoHob->PcdPciMmio32Size);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
\r
-VOID\r
-AddMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
+ PcdStatus = PcdSet64S (PcdPciIoBase, PlatformInfoHob->PcdPciIoBase);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciIoSize, PlatformInfoHob->PcdPciIoSize);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-\r
+STATIC\r
VOID\r
-AddMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
+NoexecDxeInitialization (\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
+ RETURN_STATUS Status;\r
\r
-VOID\r
-AddUntestedMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
- MemoryBase,\r
- MemorySize\r
- );\r
+ Status = PlatformNoexecDxeInitialization (PlatformInfoHob);\r
+ if (!RETURN_ERROR (Status)) {\r
+ Status = PcdSetBoolS (PcdSetNxForStack, PlatformInfoHob->PcdSetNxForStack);\r
+ ASSERT_RETURN_ERROR (Status);\r
+ }\r
}\r
\r
+static const UINT8 EmptyFdt[] = {\r
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x00, 0x48,\r
+ 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48,\r
+ 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,\r
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09,\r
+};\r
\r
VOID\r
-AddUntestedMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
-VOID\r
-MemMapInitialization (\r
+MicrovmInitialization (\r
VOID\r
)\r
{\r
- //\r
- // Create Memory Type Information HOB\r
- //\r
- BuildGuidDataHob (\r
- &gEfiMemoryTypeInformationGuid,\r
- mDefaultMemoryTypeInformation,\r
- sizeof(mDefaultMemoryTypeInformation)\r
- );\r
-\r
- //\r
- // Add PCI IO Port space available for PCI resource allocations.\r
- //\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- PcdGet64 (PcdPciIoBase),\r
- PcdGet64 (PcdPciIoSize)\r
- );\r
-\r
- //\r
- // Video memory + Legacy BIOS region\r
- //\r
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
-\r
- if (!mXen) {\r
- UINT32 TopOfLowRam;\r
- UINT32 PciBase;\r
-\r
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- //\r
- // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
- // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
- // the RAM below 4 GB exceed it.\r
- //\r
- PciBase = BASE_2GB + BASE_1GB;\r
- ASSERT (TopOfLowRam <= PciBase);\r
- } else {\r
- PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
- }\r
-\r
- //\r
- // address purpose size\r
- // ------------ -------- -------------------------\r
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
- // 0xFC000000 gap 44 MB\r
- // 0xFEC00000 IO-APIC 4 KB\r
- // 0xFEC01000 gap 1020 KB\r
- // 0xFED00000 HPET 1 KB\r
- // 0xFED00400 gap 111 KB\r
- // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
- // 0xFED20000 gap 896 KB\r
- // 0xFEE00000 LAPIC 1 MB\r
- //\r
- AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
- }\r
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
- }\r
-}\r
-\r
-EFI_STATUS\r
-GetNamedFwCfgBoolean (\r
- IN CHAR8 *FwCfgFileName,\r
- OUT BOOLEAN *Setting\r
- )\r
-{\r
- EFI_STATUS Status;\r
- FIRMWARE_CONFIG_ITEM FwCfgItem;\r
- UINTN FwCfgSize;\r
- UINT8 Value[3];\r
-\r
- Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
+ FIRMWARE_CONFIG_ITEM FdtItem;\r
+ UINTN FdtSize;\r
+ UINTN FdtPages;\r
+ EFI_STATUS Status;\r
+ UINT64 *FdtHobData;\r
+ VOID *NewBase;\r
+\r
+ Status = QemuFwCfgFindFile ("etc/fdt", &FdtItem, &FdtSize);\r
if (EFI_ERROR (Status)) {\r
- return Status;\r
+ DEBUG ((DEBUG_INFO, "%a: no etc/fdt found in fw_cfg, using dummy\n", __FUNCTION__));\r
+ FdtItem = 0;\r
+ FdtSize = sizeof (EmptyFdt);\r
}\r
- if (FwCfgSize > sizeof Value) {\r
- return EFI_BAD_BUFFER_SIZE;\r
+\r
+ FdtPages = EFI_SIZE_TO_PAGES (FdtSize);\r
+ NewBase = AllocatePages (FdtPages);\r
+ if (NewBase == NULL) {\r
+ DEBUG ((DEBUG_INFO, "%a: AllocatePages failed\n", __FUNCTION__));\r
+ return;\r
}\r
- QemuFwCfgSelectItem (FwCfgItem);\r
- QemuFwCfgReadBytes (FwCfgSize, Value);\r
-\r
- if ((FwCfgSize == 1) ||\r
- (FwCfgSize == 2 && Value[1] == '\n') ||\r
- (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
- switch (Value[0]) {\r
- case '0':\r
- case 'n':\r
- case 'N':\r
- *Setting = FALSE;\r
- return EFI_SUCCESS;\r
-\r
- case '1':\r
- case 'y':\r
- case 'Y':\r
- *Setting = TRUE;\r
- return EFI_SUCCESS;\r
-\r
- default:\r
- break;\r
- }\r
+\r
+ if (FdtItem) {\r
+ QemuFwCfgSelectItem (FdtItem);\r
+ QemuFwCfgReadBytes (FdtSize, NewBase);\r
+ } else {\r
+ CopyMem (NewBase, EmptyFdt, FdtSize);\r
}\r
- return EFI_PROTOCOL_ERROR;\r
-}\r
\r
-#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
- do { \\r
- BOOLEAN Setting; \\r
- \\r
- if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
- "opt/ovmf/" #TokenName, &Setting))) { \\r
- PcdSetBool (TokenName, Setting); \\r
- } \\r
- } while (0)\r
+ FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof (*FdtHobData));\r
+ if (FdtHobData == NULL) {\r
+ DEBUG ((DEBUG_INFO, "%a: BuildGuidHob failed\n", __FUNCTION__));\r
+ return;\r
+ }\r
\r
-VOID\r
-NoexecDxeInitialization (\r
- VOID\r
- )\r
-{\r
- UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
- UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: fdt at 0x%x (size %d)\n",\r
+ __FUNCTION__,\r
+ NewBase,\r
+ FdtSize\r
+ ));\r
+ *FdtHobData = (UINTN)NewBase;\r
}\r
\r
VOID\r
-MiscInitialization (\r
- VOID\r
+MiscInitializationForMicrovm (\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- UINTN PmCmd;\r
- UINTN Pmba;\r
- UINTN AcpiCtlReg;\r
- UINT8 AcpiEnBit;\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ ASSERT (PlatformInfoHob->HostBridgeDevId == 0xffff);\r
\r
+ DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r
//\r
// Disable A20 Mask\r
//\r
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
// S3 resume as well, so we build it unconditionally.)\r
//\r
- BuildCpuHob (mPhysMemAddressWidth, 16);\r
+ BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);\r
+\r
+ MicrovmInitialization ();\r
+ PcdStatus = PcdSet16S (\r
+ PcdOvmfHostBridgePciDevId,\r
+ MICROVM_PSEUDO_DEVICE_ID\r
+ );\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+}\r
\r
- //\r
- // Determine platform type and save Host Bridge DID to PCD\r
- //\r
- switch (mHostBridgeDevId) {\r
- case INTEL_82441_DEVICE_ID:\r
- PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
- AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
- break;\r
- case INTEL_Q35_MCH_DEVICE_ID:\r
- PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
- AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
- break;\r
- default:\r
- DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
- __FUNCTION__, mHostBridgeDevId));\r
- ASSERT (FALSE);\r
- return;\r
- }\r
- PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+VOID\r
+MiscInitialization (\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
+ )\r
+{\r
+ RETURN_STATUS PcdStatus;\r
\r
- //\r
- // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
- // has been configured (e.g., by Xen) and skip the setup here.\r
- // This matches the logic in AcpiTimerLibConstructor ().\r
- //\r
- if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
- //\r
- // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
- // 1. set PMBA\r
- //\r
- PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
-\r
- //\r
- // 2. set PCICMD/IOSE\r
- //\r
- PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
-\r
- //\r
- // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
- //\r
- PciOr8 (AcpiCtlReg, AcpiEnBit);\r
- }\r
+ PlatformMiscInitialization (PlatformInfoHob);\r
\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- //\r
- // Set Root Complex Register Block BAR\r
- //\r
- PciWrite32 (\r
- POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
- ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
- );\r
- }\r
+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-\r
VOID\r
BootModeInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- if (CmosRead8 (0xF) == 0xFE) {\r
- mBootMode = BOOT_ON_S3_RESUME;\r
+ if (PlatformCmosRead8 (0xF) == 0xFE) {\r
+ PlatformInfoHob->BootMode = BOOT_ON_S3_RESUME;\r
}\r
- CmosWrite8 (0xF, 0x00);\r
\r
- Status = PeiServicesSetBootMode (mBootMode);\r
+ PlatformCmosWrite8 (0xF, 0x00);\r
+\r
+ Status = PeiServicesSetBootMode (PlatformInfoHob->BootMode);\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = PeiServicesInstallPpi (mPpiBootMode);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
-\r
VOID\r
ReserveEmuVariableNvStore (\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS VariableStore;\r
+ EFI_PHYSICAL_ADDRESS VariableStore;\r
+ RETURN_STATUS PcdStatus;\r
\r
- //\r
- // Allocate storage for NV variables early on so it will be\r
- // at a consistent address. Since VM memory is preserved\r
- // across reboots, this allows the NV variable storage to survive\r
- // a VM reboot.\r
- //\r
- VariableStore =\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateAlignedRuntimePages (\r
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
- PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
- );\r
- DEBUG ((EFI_D_INFO,\r
- "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
- VariableStore,\r
- (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
- ));\r
- PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
-}\r
+ VariableStore = (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformReserveEmuVariableNvStore ();\r
+ PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
+\r
+ #ifdef SECURE_BOOT_FEATURE_ENABLED\r
+ PlatformInitEmuVariableNvStore ((VOID *)(UINTN)VariableStore);\r
+ #endif\r
\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+}\r
\r
VOID\r
-DebugDumpCmos (\r
+S3Verification (\r
VOID\r
)\r
{\r
- UINT32 Loop;\r
+ #if defined (MDE_CPU_X64)\r
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",\r
+ __FUNCTION__\r
+ ));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
+ __FUNCTION__\r
+ ));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",\r
+ __FUNCTION__\r
+ ));\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
+ }\r
\r
- DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
+ #endif\r
+}\r
\r
- for (Loop = 0; Loop < 0x80; Loop++) {\r
- if ((Loop % 0x10) == 0) {\r
- DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
- }\r
- DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
- if ((Loop % 0x10) == 0xf) {\r
- DEBUG ((EFI_D_INFO, "\n"));\r
- }\r
+VOID\r
+Q35BoardVerification (\r
+ VOID\r
+ )\r
+{\r
+ if (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ return;\r
}\r
+\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
+ "only DID=0x%04x (Q35) is supported\n",\r
+ __FUNCTION__,\r
+ mPlatformInfoHob.HostBridgeDevId,\r
+ INTEL_Q35_MCH_DEVICE_ID\r
+ ));\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
}\r
\r
+/**\r
+ Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
+ them to UefiCpuPkg modules. Set the MaxCpuCount field in PlatformInfoHob.\r
+**/\r
+VOID\r
+MaxCpuCountInitialization (\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
+ )\r
+{\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ PlatformMaxCpuCountInitialization (PlatformInfoHob);\r
+\r
+ PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, PlatformInfoHob->PcdCpuBootLogicalProcessorNumber);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+}\r
\r
+/**\r
+ * @brief Builds PlatformInfo Hob\r
+ */\r
VOID\r
-S3Verification (\r
+BuildPlatformInfoHob (\r
VOID\r
)\r
{\r
-#if defined (MDE_CPU_X64)\r
- if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
- DEBUG ((EFI_D_ERROR,\r
- "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
- DEBUG ((EFI_D_ERROR,\r
- "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
- __FUNCTION__));\r
- DEBUG ((EFI_D_ERROR,\r
- "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
- ASSERT (FALSE);\r
- CpuDeadLoop ();\r
- }\r
-#endif\r
+ BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &mPlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO));\r
}\r
\r
-\r
/**\r
Perform Platform PEI initialization.\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
\r
- DebugDumpCmos ();\r
+ mPlatformInfoHob.SmmSmramRequire = FeaturePcdGet (PcdSmmSmramRequire);\r
+ mPlatformInfoHob.SevEsIsEnabled = MemEncryptSevEsIsEnabled ();\r
+ mPlatformInfoHob.PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);\r
+ mPlatformInfoHob.DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
\r
- XenDetect ();\r
+ PlatformDebugDumpCmos ();\r
\r
if (QemuFwCfgS3Enabled ()) {\r
- DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
- mS3Supported = TRUE;\r
+ DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r
+ mPlatformInfoHob.S3Supported = TRUE;\r
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
\r
S3Verification ();\r
- BootModeInitialization ();\r
- AddressWidthInitialization ();\r
+ BootModeInitialization (&mPlatformInfoHob);\r
\r
- PublishPeiMemory ();\r
+ //\r
+ // Query Host Bridge DID\r
+ //\r
+ mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+ AddressWidthInitialization (&mPlatformInfoHob);\r
\r
- InitializeRamRegions ();\r
+ MaxCpuCountInitialization (&mPlatformInfoHob);\r
\r
- if (mXen) {\r
- DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
- InitializeXen ();\r
+ if (mPlatformInfoHob.SmmSmramRequire) {\r
+ Q35BoardVerification ();\r
+ Q35TsegMbytesInitialization (&mPlatformInfoHob);\r
+ Q35SmramAtDefaultSmbaseInitialization (&mPlatformInfoHob);\r
}\r
\r
- //\r
- // Query Host Bridge DID\r
- //\r
- mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+ PublishPeiMemory (&mPlatformInfoHob);\r
+\r
+ PlatformQemuUc32BaseInitialization (&mPlatformInfoHob);\r
+\r
+ InitializeRamRegions (&mPlatformInfoHob);\r
+\r
+ if (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME) {\r
+ if (!mPlatformInfoHob.SmmSmramRequire) {\r
+ ReserveEmuVariableNvStore ();\r
+ }\r
+\r
+ PeiFvInitialization (&mPlatformInfoHob);\r
+ MemTypeInfoInitialization (&mPlatformInfoHob);\r
+ MemMapInitialization (&mPlatformInfoHob);\r
+ NoexecDxeInitialization (&mPlatformInfoHob);\r
+ }\r
\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
- ReserveEmuVariableNvStore ();\r
- PeiFvInitialization ();\r
- MemMapInitialization ();\r
- NoexecDxeInitialization ();\r
+ InstallClearCacheCallback ();\r
+ AmdSevInitialize (&mPlatformInfoHob);\r
+ if (mPlatformInfoHob.HostBridgeDevId == 0xffff) {\r
+ MiscInitializationForMicrovm (&mPlatformInfoHob);\r
+ } else {\r
+ MiscInitialization (&mPlatformInfoHob);\r
}\r
\r
- MiscInitialization ();\r
+ IntelTdxInitialize ();\r
+ InstallFeatureControlCallback ();\r
+ BuildPlatformInfoHob ();\r
\r
return EFI_SUCCESS;\r
}\r
projects / mirror_edk2.git / blobdiff