#include <IndustryStandard/Pci22.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/QemuCpuHotplug.h>\r
+#include <Library/MemEncryptSevLib.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
-#include "Cmos.h"\r
+\r
+EFI_HOB_PLATFORM_INFO mPlatformInfoHob = { 0 };\r
\r
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
{\r
}\r
};\r
\r
-UINT16 mHostBridgeDevId;\r
-\r
-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
-\r
-BOOLEAN mS3Supported = FALSE;\r
-\r
-UINT32 mMaxCpuCount;\r
-\r
-VOID\r
-AddIoMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_MEMORY_MAPPED_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-VOID\r
-AddReservedMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize,\r
- BOOLEAN Cacheable\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_MEMORY_RESERVED,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- (Cacheable ?\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
- 0\r
- ) |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-VOID\r
-AddIoMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
-VOID\r
-AddMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-VOID\r
-AddMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
VOID\r
MemMapInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- UINT64 PciIoBase;\r
- UINT64 PciIoSize;\r
RETURN_STATUS PcdStatus;\r
- UINT32 TopOfLowRam;\r
- UINT64 PciExBarBase;\r
- UINT32 PciBase;\r
- UINT32 PciSize;\r
-\r
- PciIoBase = 0xC000;\r
- PciIoSize = 0x4000;\r
\r
- //\r
- // Video memory + Legacy BIOS region\r
- //\r
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+ PlatformMemMapInitialization (PlatformInfoHob);\r
\r
- if (mHostBridgeDevId == 0xffff /* microvm */) {\r
- AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r
- AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r
+ if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {\r
return;\r
}\r
\r
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
- PciExBarBase = 0;\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- //\r
- // The MMCONFIG area is expected to fall between the top of low RAM and\r
- // the base of the 32-bit PCI host aperture.\r
- //\r
- PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
- ASSERT (TopOfLowRam <= PciExBarBase);\r
- ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
- PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
- } else {\r
- ASSERT (TopOfLowRam <= mQemuUc32Base);\r
- PciBase = mQemuUc32Base;\r
- }\r
-\r
- //\r
- // address purpose size\r
- // ------------ -------- -------------------------\r
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
- // 0xFC000000 gap 44 MB\r
- // 0xFEC00000 IO-APIC 4 KB\r
- // 0xFEC01000 gap 1020 KB\r
- // 0xFED00000 HPET 1 KB\r
- // 0xFED00400 gap 111 KB\r
- // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
- // 0xFED20000 gap 896 KB\r
- // 0xFEE00000 LAPIC 1 MB\r
- //\r
- PciSize = 0xFC000000 - PciBase;\r
- AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
- PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Base, PlatformInfoHob->PcdPciMmio32Base);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Size, PlatformInfoHob->PcdPciMmio32Size);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
- //\r
- // Note: there should be an\r
- //\r
- // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
- //\r
- // call below, just like the one above for RCBA. However, Linux insists\r
- // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
- // "reserved memory" -- Linux does not content itself with a simple gap\r
- // in the memory map wherever the MCFG ACPI table points to.\r
- //\r
- // This appears to be a safety measure. The PCI Firmware Specification\r
- // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
- // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
- // [...]". (Emphasis added here.)\r
- //\r
- // Normally we add memory resource descriptor HOBs in\r
- // QemuInitializeRam(), and pre-allocate from those with memory\r
- // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
- // is most definitely not RAM; so, as an exception, cover it with\r
- // uncacheable reserved memory right here.\r
- //\r
- AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
- BuildMemoryAllocationHob (\r
- PciExBarBase,\r
- SIZE_256MB,\r
- EfiReservedMemoryType\r
- );\r
- }\r
-\r
- AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
-\r
- //\r
- // On Q35, the IO Port space is available for PCI resource allocations from\r
- // 0x6000 up.\r
- //\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- PciIoBase = 0x6000;\r
- PciIoSize = 0xA000;\r
- ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
- }\r
-\r
- //\r
- // Add PCI IO Port space available for PCI resource allocations.\r
- //\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- PciIoBase,\r
- PciIoSize\r
- );\r
- PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r
+ PcdStatus = PcdSet64S (PcdPciIoBase, PlatformInfoHob->PcdPciIoBase);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
+ PcdStatus = PcdSet64S (PcdPciIoSize, PlatformInfoHob->PcdPciIoSize);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
- do { \\r
- BOOLEAN Setting; \\r
- RETURN_STATUS PcdStatus; \\r
- \\r
- if (!RETURN_ERROR (QemuFwCfgParseBool ( \\r
- "opt/ovmf/" #TokenName, &Setting))) { \\r
- PcdStatus = PcdSetBoolS (TokenName, Setting); \\r
- ASSERT_RETURN_ERROR (PcdStatus); \\r
- } \\r
- } while (0)\r
-\r
+STATIC\r
VOID\r
NoexecDxeInitialization (\r
- VOID\r
- )\r
-{\r
- UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
-}\r
-\r
-VOID\r
-PciExBarInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- union {\r
- UINT64 Uint64;\r
- UINT32 Uint32[2];\r
- } PciExBarBase;\r
-\r
- //\r
- // We only support the 256MB size for the MMCONFIG area:\r
- // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
- //\r
- // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
- // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
- //\r
- // Note that (b) also ensures that the minimum address width we have\r
- // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
- // for DXE's page tables to cover the MMCONFIG area.\r
- //\r
- PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
- ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
- ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
-\r
- //\r
- // Clear the PCIEXBAREN bit first, before programming the high register.\r
- //\r
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
+ RETURN_STATUS Status;\r
\r
- //\r
- // Program the high register. Then program the low register, setting the\r
- // MMCONFIG area size and enabling decoding at once.\r
- //\r
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
- PciWrite32 (\r
- DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
- PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
- );\r
+ Status = PlatformNoexecDxeInitialization (PlatformInfoHob);\r
+ if (!RETURN_ERROR (Status)) {\r
+ Status = PcdSetBoolS (PcdSetNxForStack, PlatformInfoHob->PcdSetNxForStack);\r
+ ASSERT_RETURN_ERROR (Status);\r
+ }\r
}\r
\r
static const UINT8 EmptyFdt[] = {\r
}\r
\r
VOID\r
-MiscInitialization (\r
- VOID\r
+MiscInitializationForMicrovm (\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- UINTN PmCmd;\r
- UINTN Pmba;\r
- UINT32 PmbaAndVal;\r
- UINT32 PmbaOrVal;\r
- UINTN AcpiCtlReg;\r
- UINT8 AcpiEnBit;\r
RETURN_STATUS PcdStatus;\r
\r
+ ASSERT (PlatformInfoHob->HostBridgeDevId == 0xffff);\r
+\r
+ DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r
//\r
// Disable A20 Mask\r
//\r
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
// S3 resume as well, so we build it unconditionally.)\r
//\r
- BuildCpuHob (mPhysMemAddressWidth, 16);\r
-\r
- //\r
- // Determine platform type and save Host Bridge DID to PCD\r
- //\r
- switch (mHostBridgeDevId) {\r
- case INTEL_82441_DEVICE_ID:\r
- PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
- PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
- PmbaOrVal = PIIX4_PMBA_VALUE;\r
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
- AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
- break;\r
- case INTEL_Q35_MCH_DEVICE_ID:\r
- PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
- PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
- PmbaOrVal = ICH9_PMBASE_VALUE;\r
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
- AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
- break;\r
- case 0xffff: /* microvm */\r
- DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r
- MicrovmInitialization ();\r
- PcdStatus = PcdSet16S (\r
- PcdOvmfHostBridgePciDevId,\r
- MICROVM_PSEUDO_DEVICE_ID\r
- );\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
- return;\r
- case CLOUDHV_DEVICE_ID:\r
- DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));\r
- PcdStatus = PcdSet16S (\r
- PcdOvmfHostBridgePciDevId,\r
- CLOUDHV_DEVICE_ID\r
- );\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
- return;\r
- default:\r
- DEBUG ((\r
- DEBUG_ERROR,\r
- "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
- __FUNCTION__,\r
- mHostBridgeDevId\r
- ));\r
- ASSERT (FALSE);\r
- return;\r
- }\r
+ BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);\r
\r
- PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+ MicrovmInitialization ();\r
+ PcdStatus = PcdSet16S (\r
+ PcdOvmfHostBridgePciDevId,\r
+ MICROVM_PSEUDO_DEVICE_ID\r
+ );\r
ASSERT_RETURN_ERROR (PcdStatus);\r
+}\r
\r
- //\r
- // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has\r
- // been configured and skip the setup here. This matches the logic in\r
- // AcpiTimerLibConstructor ().\r
- //\r
- if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
- //\r
- // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
- // 1. set PMBA\r
- //\r
- PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
-\r
- //\r
- // 2. set PCICMD/IOSE\r
- //\r
- PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
-\r
- //\r
- // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
- //\r
- PciOr8 (AcpiCtlReg, AcpiEnBit);\r
- }\r
+VOID\r
+MiscInitialization (\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
+ )\r
+{\r
+ RETURN_STATUS PcdStatus;\r
\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- //\r
- // Set Root Complex Register Block BAR\r
- //\r
- PciWrite32 (\r
- POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
- ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
- );\r
-\r
- //\r
- // Set PCI Express Register Range Base Address\r
- //\r
- PciExBarInitialization ();\r
- }\r
+ PlatformMiscInitialization (PlatformInfoHob);\r
+\r
+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
VOID\r
BootModeInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
EFI_STATUS Status;\r
\r
- if (CmosRead8 (0xF) == 0xFE) {\r
- mBootMode = BOOT_ON_S3_RESUME;\r
+ if (PlatformCmosRead8 (0xF) == 0xFE) {\r
+ PlatformInfoHob->BootMode = BOOT_ON_S3_RESUME;\r
}\r
\r
- CmosWrite8 (0xF, 0x00);\r
+ PlatformCmosWrite8 (0xF, 0x00);\r
\r
- Status = PeiServicesSetBootMode (mBootMode);\r
+ Status = PeiServicesSetBootMode (PlatformInfoHob->BootMode);\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = PeiServicesInstallPpi (mPpiBootMode);\r
EFI_PHYSICAL_ADDRESS VariableStore;\r
RETURN_STATUS PcdStatus;\r
\r
- //\r
- // Allocate storage for NV variables early on so it will be\r
- // at a consistent address. Since VM memory is preserved\r
- // across reboots, this allows the NV variable storage to survive\r
- // a VM reboot.\r
- //\r
- VariableStore =\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateRuntimePages (\r
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
- );\r
- DEBUG ((\r
- DEBUG_INFO,\r
- "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
- VariableStore,\r
- (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
- ));\r
- PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
-}\r
+ VariableStore = (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformReserveEmuVariableNvStore ();\r
+ PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
\r
-VOID\r
-DebugDumpCmos (\r
- VOID\r
- )\r
-{\r
- UINT32 Loop;\r
-\r
- DEBUG ((DEBUG_INFO, "CMOS:\n"));\r
-\r
- for (Loop = 0; Loop < 0x80; Loop++) {\r
- if ((Loop % 0x10) == 0) {\r
- DEBUG ((DEBUG_INFO, "%02x:", Loop));\r
- }\r
+ #ifdef SECURE_BOOT_FEATURE_ENABLED\r
+ PlatformInitEmuVariableNvStore ((VOID *)(UINTN)VariableStore);\r
+ #endif\r
\r
- DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));\r
- if ((Loop % 0x10) == 0xf) {\r
- DEBUG ((DEBUG_INFO, "\n"));\r
- }\r
- }\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
VOID\r
)\r
{\r
#if defined (MDE_CPU_X64)\r
- if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) {\r
DEBUG ((\r
DEBUG_ERROR,\r
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",\r
VOID\r
)\r
{\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ if (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
return;\r
}\r
\r
"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
"only DID=0x%04x (Q35) is supported\n",\r
__FUNCTION__,\r
- mHostBridgeDevId,\r
+ mPlatformInfoHob.HostBridgeDevId,\r
INTEL_Q35_MCH_DEVICE_ID\r
));\r
ASSERT (FALSE);\r
\r
/**\r
Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
- them to UefiCpuPkg modules. Set the mMaxCpuCount variable.\r
+ them to UefiCpuPkg modules. Set the MaxCpuCount field in PlatformInfoHob.\r
**/\r
VOID\r
MaxCpuCountInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- UINT16 BootCpuCount;\r
RETURN_STATUS PcdStatus;\r
\r
- //\r
- // Try to fetch the boot CPU count.\r
- //\r
- QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
- BootCpuCount = QemuFwCfgRead16 ();\r
- if (BootCpuCount == 0) {\r
- //\r
- // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let\r
- // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or\r
- // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached\r
- // first).\r
- //\r
- DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));\r
- mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
- } else {\r
- //\r
- // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to\r
- // (BootCpuCount - 1) precisely, regardless of timeout.\r
- //\r
- // Now try to fetch the possible CPU count.\r
- //\r
- UINTN CpuHpBase;\r
- UINT32 CmdData2;\r
-\r
- CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r
- ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);\r
-\r
- //\r
- // If only legacy mode is available in the CPU hotplug register block, or\r
- // the register block is completely missing, then the writes below are\r
- // no-ops.\r
- //\r
- // 1. Switch the hotplug register block to modern mode.\r
- //\r
- IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r
- //\r
- // 2. Select a valid CPU for deterministic reading of\r
- // QEMU_CPUHP_R_CMD_DATA2.\r
- //\r
- // CPU#0 is always valid; it is the always present and non-removable\r
- // BSP.\r
- //\r
- IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r
- //\r
- // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to\r
- // read as zero, and which does not invalidate the selector. (The\r
- // selector may change, but it must not become invalid.)\r
- //\r
- // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.\r
- //\r
- IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);\r
- //\r
- // 4. Read QEMU_CPUHP_R_CMD_DATA2.\r
- //\r
- // If the register block is entirely missing, then this is an unassigned\r
- // IO read, returning all-bits-one.\r
- //\r
- // If only legacy mode is available, then bit#0 stands for CPU#0 in the\r
- // "CPU present bitmap". CPU#0 is always present.\r
- //\r
- // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning\r
- // all-bits-zero), or it is specified to read as zero after the above\r
- // steps. Both cases confirm modern mode.\r
- //\r
- CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);\r
- DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));\r
- if (CmdData2 != 0) {\r
- //\r
- // QEMU doesn't support the modern CPU hotplug interface. Assume that the\r
- // possible CPU count equals the boot CPU count (precluding hotplug).\r
- //\r
- DEBUG ((\r
- DEBUG_WARN,\r
- "%a: modern CPU hotplug interface unavailable\n",\r
- __FUNCTION__\r
- ));\r
- mMaxCpuCount = BootCpuCount;\r
- } else {\r
- //\r
- // Grab the possible CPU count from the modern CPU hotplug interface.\r
- //\r
- UINT32 Present, Possible, Selected;\r
-\r
- Present = 0;\r
- Possible = 0;\r
-\r
- //\r
- // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures\r
- // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,\r
- // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending\r
- // hotplug events; therefore, select CPU#0 forcibly.\r
- //\r
- IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r
-\r
- do {\r
- UINT8 CpuStatus;\r
-\r
- //\r
- // Read the status of the currently selected CPU. This will help with a\r
- // sanity check against "BootCpuCount".\r
- //\r
- CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);\r
- if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {\r
- ++Present;\r
- }\r
-\r
- //\r
- // Attempt to select the next CPU.\r
- //\r
- ++Possible;\r
- IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r
- //\r
- // If the selection is successful, then the following read will return\r
- // the selector (which we know is positive at this point). Otherwise,\r
- // the read will return 0.\r
- //\r
- Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);\r
- ASSERT (Selected == Possible || Selected == 0);\r
- } while (Selected > 0);\r
-\r
- //\r
- // Sanity check: fw_cfg and the modern CPU hotplug interface should\r
- // return the same boot CPU count.\r
- //\r
- if (BootCpuCount != Present) {\r
- DEBUG ((\r
- DEBUG_WARN,\r
- "%a: QEMU v2.7 reset bug: BootCpuCount=%d "\r
- "Present=%u\n",\r
- __FUNCTION__,\r
- BootCpuCount,\r
- Present\r
- ));\r
- //\r
- // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus\r
- // platform reset (including S3), was corrected in QEMU commit\r
- // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added\r
- // CPUs", 2016-11-16), part of release v2.8.0.\r
- //\r
- BootCpuCount = (UINT16)Present;\r
- }\r
-\r
- mMaxCpuCount = Possible;\r
- }\r
- }\r
+ PlatformMaxCpuCountInitialization (PlatformInfoHob);\r
\r
- DEBUG ((\r
- DEBUG_INFO,\r
- "%a: BootCpuCount=%d mMaxCpuCount=%u\n",\r
- __FUNCTION__,\r
- BootCpuCount,\r
- mMaxCpuCount\r
- ));\r
- ASSERT (BootCpuCount <= mMaxCpuCount);\r
-\r
- PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);\r
+ PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, PlatformInfoHob->PcdCpuBootLogicalProcessorNumber);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);\r
+ PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
+/**\r
+ * @brief Builds PlatformInfo Hob\r
+ */\r
+VOID\r
+BuildPlatformInfoHob (\r
+ VOID\r
+ )\r
+{\r
+ BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &mPlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO));\r
+}\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
\r
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
\r
- DebugDumpCmos ();\r
+ mPlatformInfoHob.SmmSmramRequire = FeaturePcdGet (PcdSmmSmramRequire);\r
+ mPlatformInfoHob.SevEsIsEnabled = MemEncryptSevEsIsEnabled ();\r
+ mPlatformInfoHob.PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);\r
+ mPlatformInfoHob.DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+\r
+ PlatformDebugDumpCmos ();\r
\r
if (QemuFwCfgS3Enabled ()) {\r
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r
- mS3Supported = TRUE;\r
- Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
+ mPlatformInfoHob.S3Supported = TRUE;\r
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
S3Verification ();\r
- BootModeInitialization ();\r
- AddressWidthInitialization ();\r
+ BootModeInitialization (&mPlatformInfoHob);\r
\r
//\r
// Query Host Bridge DID\r
//\r
- mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+ mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+ AddressWidthInitialization (&mPlatformInfoHob);\r
\r
- MaxCpuCountInitialization ();\r
+ MaxCpuCountInitialization (&mPlatformInfoHob);\r
\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ if (mPlatformInfoHob.SmmSmramRequire) {\r
Q35BoardVerification ();\r
- Q35TsegMbytesInitialization ();\r
- Q35SmramAtDefaultSmbaseInitialization ();\r
+ Q35TsegMbytesInitialization (&mPlatformInfoHob);\r
+ Q35SmramAtDefaultSmbaseInitialization (&mPlatformInfoHob);\r
}\r
\r
- PublishPeiMemory ();\r
+ PublishPeiMemory (&mPlatformInfoHob);\r
\r
- QemuUc32BaseInitialization ();\r
+ PlatformQemuUc32BaseInitialization (&mPlatformInfoHob);\r
\r
- InitializeRamRegions ();\r
+ InitializeRamRegions (&mPlatformInfoHob);\r
\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
- if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ if (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME) {\r
+ if (!mPlatformInfoHob.SmmSmramRequire) {\r
ReserveEmuVariableNvStore ();\r
}\r
\r
- PeiFvInitialization ();\r
- MemTypeInfoInitialization ();\r
- MemMapInitialization ();\r
- NoexecDxeInitialization ();\r
+ PeiFvInitialization (&mPlatformInfoHob);\r
+ MemTypeInfoInitialization (&mPlatformInfoHob);\r
+ MemMapInitialization (&mPlatformInfoHob);\r
+ NoexecDxeInitialization (&mPlatformInfoHob);\r
}\r
\r
InstallClearCacheCallback ();\r
- AmdSevInitialize ();\r
- MiscInitialization ();\r
+ AmdSevInitialize (&mPlatformInfoHob);\r
+ if (mPlatformInfoHob.HostBridgeDevId == 0xffff) {\r
+ MiscInitializationForMicrovm (&mPlatformInfoHob);\r
+ } else {\r
+ MiscInitialization (&mPlatformInfoHob);\r
+ }\r
+\r
+ IntelTdxInitialize ();\r
InstallFeatureControlCallback ();\r
+ BuildPlatformInfoHob ();\r
\r
return EFI_SUCCESS;\r
}\r
projects / mirror_edk2.git / blobdiff