ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
+STATIC\r
VOID\r
NoexecDxeInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
RETURN_STATUS Status;\r
\r
- Status = PlatformNoexecDxeInitialization (&mPlatformInfoHob);\r
+ Status = PlatformNoexecDxeInitialization (PlatformInfoHob);\r
if (!RETURN_ERROR (Status)) {\r
- Status = PcdSetBoolS (PcdSetNxForStack, mPlatformInfoHob.PcdSetNxForStack);\r
+ Status = PcdSetBoolS (PcdSetNxForStack, PlatformInfoHob->PcdSetNxForStack);\r
ASSERT_RETURN_ERROR (Status);\r
}\r
}\r
EFI_PHYSICAL_ADDRESS VariableStore;\r
RETURN_STATUS PcdStatus;\r
\r
- //\r
- // Allocate storage for NV variables early on so it will be\r
- // at a consistent address. Since VM memory is preserved\r
- // across reboots, this allows the NV variable storage to survive\r
- // a VM reboot.\r
- //\r
- VariableStore =\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateRuntimePages (\r
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
- );\r
- DEBUG ((\r
- DEBUG_INFO,\r
- "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
- VariableStore,\r
- (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
- ));\r
- PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
+ VariableStore = (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformReserveEmuVariableNvStore ();\r
+ PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
+\r
+ #ifdef SECURE_BOOT_FEATURE_ENABLED\r
+ PlatformInitEmuVariableNvStore ((VOID *)(UINTN)VariableStore);\r
+ #endif\r
+\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
\r
S3Verification ();\r
BootModeInitialization (&mPlatformInfoHob);\r
- AddressWidthInitialization (&mPlatformInfoHob);\r
\r
//\r
// Query Host Bridge DID\r
//\r
mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+ AddressWidthInitialization (&mPlatformInfoHob);\r
\r
MaxCpuCountInitialization (&mPlatformInfoHob);\r
\r
if (mPlatformInfoHob.SmmSmramRequire) {\r
Q35BoardVerification ();\r
- Q35TsegMbytesInitialization ();\r
- Q35SmramAtDefaultSmbaseInitialization ();\r
+ Q35TsegMbytesInitialization (&mPlatformInfoHob);\r
+ Q35SmramAtDefaultSmbaseInitialization (&mPlatformInfoHob);\r
}\r
\r
- PublishPeiMemory ();\r
+ PublishPeiMemory (&mPlatformInfoHob);\r
\r
PlatformQemuUc32BaseInitialization (&mPlatformInfoHob);\r
\r
ReserveEmuVariableNvStore ();\r
}\r
\r
- PeiFvInitialization ();\r
- MemTypeInfoInitialization ();\r
+ PeiFvInitialization (&mPlatformInfoHob);\r
+ MemTypeInfoInitialization (&mPlatformInfoHob);\r
MemMapInitialization (&mPlatformInfoHob);\r
- NoexecDxeInitialization ();\r
+ NoexecDxeInitialization (&mPlatformInfoHob);\r
}\r
\r
InstallClearCacheCallback ();\r
- AmdSevInitialize ();\r
+ AmdSevInitialize (&mPlatformInfoHob);\r
if (mPlatformInfoHob.HostBridgeDevId == 0xffff) {\r
MiscInitializationForMicrovm (&mPlatformInfoHob);\r
} else {\r