AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
if (!mXen) {\r
- UINT32 TopOfLowRam;\r
UINT64 PciExBarBase;\r
UINT32 PciBase;\r
UINT32 PciSize;\r
\r
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
PciExBarBase = 0;\r
- PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+ PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// The 32-bit PCI host aperture is expected to fall between the top of\r