CryptoPkg CLANG35: add -std=c99 to dodge OpenSSL C atomics issue

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 9c013613a1a0b35517bd5b7da039a5ede5c304b8..c064b4ed9b8fb5e85ef3c9805a4dc4bcb40e1544 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -174,24 +174,21 @@ MemMapInitialization (
   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
 \r
   if (!mXen) {\r
-    UINT32  TopOfLowRam;\r
     UINT64  PciExBarBase;\r
     UINT32  PciBase;\r
     UINT32  PciSize;\r
 \r
-    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     PciExBarBase = 0;\r
-    PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+    PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       //\r
-      // The MMCONFIG area is expected to fall between the top of low RAM and\r
-      // the base of the 32-bit PCI host aperture.\r
+      // The 32-bit PCI host aperture is expected to fall between the top of\r
+      // low RAM and the base of the MMCONFIG area.\r
       //\r
       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
-      ASSERT (TopOfLowRam <= PciExBarBase);\r
+      ASSERT (PciBase < PciExBarBase);\r
       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
-      PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
-      PciSize = 0xFC000000 - PciBase;\r
+      PciSize = (UINT32)(PciExBarBase - PciBase);\r
     } else {\r
       PciSize = 0xFC000000 - PciBase;\r
     }\r