CryptoPkg CLANG35: add -std=c99 to dodge OpenSSL C atomics issue

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index c6e1106c9ed01ef790ad9947497e9192cf34dd5a..c064b4ed9b8fb5e85ef3c9805a4dc4bcb40e1544 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -4,13 +4,7 @@
   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
 \r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -32,6 +26,7 @@
 #include <Library/PeimEntryPoint.h>\r
 #include <Library/PeiServicesLib.h>\r
 #include <Library/QemuFwCfgLib.h>\r
+#include <Library/QemuFwCfgS3Lib.h>\r
 #include <Library/ResourcePublicationLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
@@ -68,6 +63,7 @@ EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
 \r
 BOOLEAN mS3Supported = FALSE;\r
 \r
+UINT32 mMaxCpuCount;\r
 \r
 VOID\r
 AddIoMemoryBaseSizeHob (\r
@@ -178,24 +174,23 @@ MemMapInitialization (
   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
 \r
   if (!mXen) {\r
-    UINT32  TopOfLowRam;\r
     UINT64  PciExBarBase;\r
     UINT32  PciBase;\r
     UINT32  PciSize;\r
 \r
-    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     PciExBarBase = 0;\r
+    PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       //\r
-      // The MMCONFIG area is expected to fall between the top of low RAM and\r
-      // the base of the 32-bit PCI host aperture.\r
+      // The 32-bit PCI host aperture is expected to fall between the top of\r
+      // low RAM and the base of the MMCONFIG area.\r
       //\r
       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
-      ASSERT (TopOfLowRam <= PciExBarBase);\r
+      ASSERT (PciBase < PciExBarBase);\r
       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
-      PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
+      PciSize = (UINT32)(PciExBarBase - PciBase);\r
     } else {\r
-      PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+      PciSize = 0xFC000000 - PciBase;\r
     }\r
 \r
     //\r
@@ -211,7 +206,6 @@ MemMapInitialization (
     // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
-    PciSize = 0xFC000000 - PciBase;\r
     AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
     ASSERT_RETURN_ERROR (PcdStatus);\r
@@ -511,9 +505,8 @@ ReserveEmuVariableNvStore (
   //\r
   VariableStore =\r
     (EFI_PHYSICAL_ADDRESS)(UINTN)\r
-      AllocateAlignedRuntimePages (\r
-        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
-        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+      AllocateRuntimePages (\r
+        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
         );\r
   DEBUG ((EFI_D_INFO,\r
           "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
@@ -567,6 +560,47 @@ S3Verification (
 }\r
 \r
 \r
+/**\r
+  Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r
+  Set the mMaxCpuCount variable.\r
+**/\r
+VOID\r
+MaxCpuCountInitialization (\r
+  VOID\r
+  )\r
+{\r
+  UINT16        ProcessorCount;\r
+  RETURN_STATUS PcdStatus;\r
+\r
+  QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
+  ProcessorCount = QemuFwCfgRead16 ();\r
+  //\r
+  // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r
+  // from the PCD default. No change to PCDs.\r
+  //\r
+  if (ProcessorCount == 0) {\r
+    mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+    return;\r
+  }\r
+  //\r
+  // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r
+  //\r
+  mMaxCpuCount = ProcessorCount;\r
+  //\r
+  // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r
+  // to wait, in the initial AP bringup, exactly as long as it takes for all of\r
+  // the APs to report in. For this, we set the longest representable timeout\r
+  // (approx. 71 minutes).\r
+  //\r
+  PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
+  PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
+  DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r
+    ProcessorCount));\r
+}\r
+\r
+\r
 /**\r
   Perform Platform PEI initialization.\r
 \r
@@ -585,7 +619,7 @@ InitializePlatform (
 {\r
   EFI_STATUS    Status;\r
 \r
-  DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
+  DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
 \r
   DebugDumpCmos ();\r
 \r
@@ -601,6 +635,16 @@ InitializePlatform (
   S3Verification ();\r
   BootModeInitialization ();\r
   AddressWidthInitialization ();\r
+  MaxCpuCountInitialization ();\r
+\r
+  //\r
+  // Query Host Bridge DID\r
+  //\r
+  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+\r
+  if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+    Q35TsegMbytesInitialization ();\r
+  }\r
 \r
   PublishPeiMemory ();\r
 \r
@@ -611,18 +655,17 @@ InitializePlatform (
     InitializeXen ();\r
   }\r
 \r
-  //\r
-  // Query Host Bridge DID\r
-  //\r
-  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
-\r
   if (mBootMode != BOOT_ON_S3_RESUME) {\r
-    ReserveEmuVariableNvStore ();\r
+    if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
+      ReserveEmuVariableNvStore ();\r
+    }\r
     PeiFvInitialization ();\r
     MemMapInitialization ();\r
     NoexecDxeInitialization ();\r
   }\r
 \r
+  InstallClearCacheCallback ();\r
+  AmdSevInitialize ();\r
   MiscInitialization ();\r
   InstallFeatureControlCallback ();\r
 \r