BaseTools/GenBootSector: Fix file handles not being closed

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index a5654a51183bf36c2a8d68e78b0f91c23ad77e6d..c6e1106c9ed01ef790ad9947497e9192cf34dd5a 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -156,6 +156,13 @@ MemMapInitialization (
   VOID\r
   )\r
 {\r
+  UINT64        PciIoBase;\r
+  UINT64        PciIoSize;\r
+  RETURN_STATUS PcdStatus;\r
+\r
+  PciIoBase = 0xC000;\r
+  PciIoSize = 0x4000;\r
+\r
   //\r
   // Create Memory Type Information HOB\r
   //\r
@@ -165,17 +172,6 @@ MemMapInitialization (
     sizeof(mDefaultMemoryTypeInformation)\r
     );\r
 \r
-  //\r
-  // Add PCI IO Port space available for PCI resource allocations.\r
-  //\r
-  BuildResourceDescriptorHob (\r
-    EFI_RESOURCE_IO,\r
-    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
-    PcdGet64 (PcdPciIoBase),\r
-    PcdGet64 (PcdPciIoSize)\r
-    );\r
-\r
   //\r
   // Video memory + Legacy BIOS region\r
   //\r
@@ -217,8 +213,11 @@ MemMapInitialization (
     //\r
     PciSize = 0xFC000000 - PciBase;\r
     AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
-    PcdSet64 (PcdPciMmio32Base, PciBase);\r
-    PcdSet64 (PcdPciMmio32Size, PciSize);\r
+    PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
+    ASSERT_RETURN_ERROR (PcdStatus);\r
+    PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
+    ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
@@ -249,7 +248,32 @@ MemMapInitialization (
         EfiReservedMemoryType);\r
     }\r
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+\r
+    //\r
+    // On Q35, the IO Port space is available for PCI resource allocations from\r
+    // 0x6000 up.\r
+    //\r
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+      PciIoBase = 0x6000;\r
+      PciIoSize = 0xA000;\r
+      ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
+    }\r
   }\r
+\r
+  //\r
+  // Add PCI IO Port space available for PCI resource allocations.\r
+  //\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_IO,\r
+    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+    PciIoBase,\r
+    PciIoSize\r
+    );\r
+  PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
+  PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
 }\r
 \r
 EFI_STATUS\r
@@ -298,11 +322,13 @@ GetNamedFwCfgBoolean (
 \r
 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \\r
           do {                                                      \\r
-            BOOLEAN Setting;                                        \\r
+            BOOLEAN       Setting;                                  \\r
+            RETURN_STATUS PcdStatus;                                \\r
                                                                     \\r
             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \\r
                               "opt/ovmf/" #TokenName, &Setting))) { \\r
-              PcdSetBool (TokenName, Setting);                      \\r
+              PcdStatus = PcdSetBoolS (TokenName, Setting);         \\r
+              ASSERT_RETURN_ERROR (PcdStatus);                      \\r
             }                                                       \\r
           } while (0)\r
 \r
@@ -361,12 +387,13 @@ MiscInitialization (
   VOID\r
   )\r
 {\r
-  UINTN  PmCmd;\r
-  UINTN  Pmba;\r
-  UINT32 PmbaAndVal;\r
-  UINT32 PmbaOrVal;\r
-  UINTN  AcpiCtlReg;\r
-  UINT8  AcpiEnBit;\r
+  UINTN         PmCmd;\r
+  UINTN         Pmba;\r
+  UINT32        PmbaAndVal;\r
+  UINT32        PmbaOrVal;\r
+  UINTN         AcpiCtlReg;\r
+  UINT8         AcpiEnBit;\r
+  RETURN_STATUS PcdStatus;\r
 \r
   //\r
   // Disable A20 Mask\r
@@ -406,7 +433,8 @@ MiscInitialization (
       ASSERT (FALSE);\r
       return;\r
   }\r
-  PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+  PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
 \r
   //\r
   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
@@ -473,6 +501,7 @@ ReserveEmuVariableNvStore (
   )\r
 {\r
   EFI_PHYSICAL_ADDRESS VariableStore;\r
+  RETURN_STATUS        PcdStatus;\r
 \r
   //\r
   // Allocate storage for NV variables early on so it will be\r
@@ -491,7 +520,8 @@ ReserveEmuVariableNvStore (
           VariableStore,\r
           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
         ));\r
-  PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
+  PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
+  ASSERT_RETURN_ERROR (PcdStatus);\r
 }\r
 \r
 \r
@@ -594,6 +624,7 @@ InitializePlatform (
   }\r
 \r
   MiscInitialization ();\r
+  InstallFeatureControlCallback ();\r
 \r
   return EFI_SUCCESS;\r
 }\r