//\r
// The Library classes this module consumes\r
//\r
+#include <Library/BaseMemoryLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/I440FxPiix4.h>\r
+#include <IndustryStandard/Microvm.h>\r
#include <IndustryStandard/Pci22.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/QemuCpuHotplug.h>\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
-EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
{\r
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
&gEfiPeiMasterBootModePpiGuid,\r
}\r
};\r
\r
+UINT16 mHostBridgeDevId;\r
\r
-UINT16 mHostBridgeDevId;\r
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
\r
-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+BOOLEAN mS3Supported = FALSE;\r
\r
-BOOLEAN mS3Supported = FALSE;\r
-\r
-UINT32 mMaxCpuCount;\r
+UINT32 mMaxCpuCount;\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
)\r
{\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_MEMORY_MAPPED_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
MemoryBase,\r
MemorySize\r
);\r
\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize,\r
- BOOLEAN Cacheable\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize,\r
+ BOOLEAN Cacheable\r
)\r
{\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_MEMORY_RESERVED,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- (Cacheable ?\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
- 0\r
- ) |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ (Cacheable ?\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
+ 0\r
+ ) |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
MemoryBase,\r
MemorySize\r
);\r
\r
VOID\r
AddIoMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
)\r
{\r
AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
-\r
VOID\r
AddMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
)\r
{\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
MemoryBase,\r
MemorySize\r
);\r
}\r
\r
-\r
VOID\r
AddMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
)\r
{\r
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
-\r
VOID\r
MemMapInitialization (\r
VOID\r
)\r
{\r
- UINT64 PciIoBase;\r
- UINT64 PciIoSize;\r
- RETURN_STATUS PcdStatus;\r
+ UINT64 PciIoBase;\r
+ UINT64 PciIoSize;\r
+ RETURN_STATUS PcdStatus;\r
+ UINT32 TopOfLowRam;\r
+ UINT64 PciExBarBase;\r
+ UINT32 PciBase;\r
+ UINT32 PciSize;\r
\r
PciIoBase = 0xC000;\r
PciIoSize = 0x4000;\r
//\r
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
- if (!mXen) {\r
- UINT32 TopOfLowRam;\r
- UINT64 PciExBarBase;\r
- UINT32 PciBase;\r
- UINT32 PciSize;\r
-\r
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
- PciExBarBase = 0;\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- //\r
- // The MMCONFIG area is expected to fall between the top of low RAM and\r
- // the base of the 32-bit PCI host aperture.\r
- //\r
- PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
- ASSERT (TopOfLowRam <= PciExBarBase);\r
- ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
- PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
- } else {\r
- ASSERT (TopOfLowRam <= mQemuUc32Base);\r
- PciBase = mQemuUc32Base;\r
- }\r
+ if (mHostBridgeDevId == 0xffff /* microvm */) {\r
+ AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r
+ AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r
+ return;\r
+ }\r
\r
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+ PciExBarBase = 0;\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
- // address purpose size\r
- // ------------ -------- -------------------------\r
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
- // 0xFC000000 gap 44 MB\r
- // 0xFEC00000 IO-APIC 4 KB\r
- // 0xFEC01000 gap 1020 KB\r
- // 0xFED00000 HPET 1 KB\r
- // 0xFED00400 gap 111 KB\r
- // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
- // 0xFED20000 gap 896 KB\r
- // 0xFEE00000 LAPIC 1 MB\r
- //\r
- PciSize = 0xFC000000 - PciBase;\r
- AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
- PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
-\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
- //\r
- // Note: there should be an\r
- //\r
- // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
- //\r
- // call below, just like the one above for RCBA. However, Linux insists\r
- // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
- // "reserved memory" -- Linux does not content itself with a simple gap\r
- // in the memory map wherever the MCFG ACPI table points to.\r
- //\r
- // This appears to be a safety measure. The PCI Firmware Specification\r
- // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
- // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
- // [...]". (Emphasis added here.)\r
- //\r
- // Normally we add memory resource descriptor HOBs in\r
- // QemuInitializeRam(), and pre-allocate from those with memory\r
- // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
- // is most definitely not RAM; so, as an exception, cover it with\r
- // uncacheable reserved memory right here.\r
- //\r
- AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
- BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r
- EfiReservedMemoryType);\r
- }\r
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+ // The MMCONFIG area is expected to fall between the top of low RAM and\r
+ // the base of the 32-bit PCI host aperture.\r
+ //\r
+ PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+ ASSERT (TopOfLowRam <= PciExBarBase);\r
+ ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
+ PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
+ } else {\r
+ ASSERT (TopOfLowRam <= mQemuUc32Base);\r
+ PciBase = mQemuUc32Base;\r
+ }\r
+\r
+ //\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 111 KB\r
+ // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
+ // 0xFED20000 gap 896 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
+ //\r
+ PciSize = 0xFC000000 - PciBase;\r
+ AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
//\r
- // On Q35, the IO Port space is available for PCI resource allocations from\r
- // 0x6000 up.\r
+ // Note: there should be an\r
//\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- PciIoBase = 0x6000;\r
- PciIoSize = 0xA000;\r
- ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
- }\r
+ // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
+ //\r
+ // call below, just like the one above for RCBA. However, Linux insists\r
+ // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
+ // "reserved memory" -- Linux does not content itself with a simple gap\r
+ // in the memory map wherever the MCFG ACPI table points to.\r
+ //\r
+ // This appears to be a safety measure. The PCI Firmware Specification\r
+ // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
+ // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
+ // [...]". (Emphasis added here.)\r
+ //\r
+ // Normally we add memory resource descriptor HOBs in\r
+ // QemuInitializeRam(), and pre-allocate from those with memory\r
+ // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
+ // is most definitely not RAM; so, as an exception, cover it with\r
+ // uncacheable reserved memory right here.\r
+ //\r
+ AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
+ BuildMemoryAllocationHob (\r
+ PciExBarBase,\r
+ SIZE_256MB,\r
+ EfiReservedMemoryType\r
+ );\r
+ }\r
+\r
+ AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+\r
+ //\r
+ // On Q35, the IO Port space is available for PCI resource allocations from\r
+ // 0x6000 up.\r
+ //\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ PciIoBase = 0x6000;\r
+ PciIoSize = 0xA000;\r
+ ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
}\r
\r
//\r
)\r
{\r
union {\r
- UINT64 Uint64;\r
- UINT32 Uint32[2];\r
+ UINT64 Uint64;\r
+ UINT32 Uint32[2];\r
} PciExBarBase;\r
\r
//\r
);\r
}\r
\r
+static const UINT8 EmptyFdt[] = {\r
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x00, 0x48,\r
+ 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48,\r
+ 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,\r
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09,\r
+};\r
+\r
+VOID\r
+MicrovmInitialization (\r
+ VOID\r
+ )\r
+{\r
+ FIRMWARE_CONFIG_ITEM FdtItem;\r
+ UINTN FdtSize;\r
+ UINTN FdtPages;\r
+ EFI_STATUS Status;\r
+ UINT64 *FdtHobData;\r
+ VOID *NewBase;\r
+\r
+ Status = QemuFwCfgFindFile ("etc/fdt", &FdtItem, &FdtSize);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_INFO, "%a: no etc/fdt found in fw_cfg, using dummy\n", __FUNCTION__));\r
+ FdtItem = 0;\r
+ FdtSize = sizeof (EmptyFdt);\r
+ }\r
+\r
+ FdtPages = EFI_SIZE_TO_PAGES (FdtSize);\r
+ NewBase = AllocatePages (FdtPages);\r
+ if (NewBase == NULL) {\r
+ DEBUG ((DEBUG_INFO, "%a: AllocatePages failed\n", __FUNCTION__));\r
+ return;\r
+ }\r
+\r
+ if (FdtItem) {\r
+ QemuFwCfgSelectItem (FdtItem);\r
+ QemuFwCfgReadBytes (FdtSize, NewBase);\r
+ } else {\r
+ CopyMem (NewBase, EmptyFdt, FdtSize);\r
+ }\r
+\r
+ FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof (*FdtHobData));\r
+ if (FdtHobData == NULL) {\r
+ DEBUG ((DEBUG_INFO, "%a: BuildGuidHob failed\n", __FUNCTION__));\r
+ return;\r
+ }\r
+\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: fdt at 0x%x (size %d)\n",\r
+ __FUNCTION__,\r
+ NewBase,\r
+ FdtSize\r
+ ));\r
+ *FdtHobData = (UINTN)NewBase;\r
+}\r
+\r
VOID\r
MiscInitialization (\r
VOID\r
)\r
{\r
- UINTN PmCmd;\r
- UINTN Pmba;\r
- UINT32 PmbaAndVal;\r
- UINT32 PmbaOrVal;\r
- UINTN AcpiCtlReg;\r
- UINT8 AcpiEnBit;\r
- RETURN_STATUS PcdStatus;\r
+ UINTN PmCmd;\r
+ UINTN Pmba;\r
+ UINT32 PmbaAndVal;\r
+ UINT32 PmbaOrVal;\r
+ UINTN AcpiCtlReg;\r
+ UINT8 AcpiEnBit;\r
+ RETURN_STATUS PcdStatus;\r
\r
//\r
// Disable A20 Mask\r
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
+ case 0xffff: /* microvm */\r
+ DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r
+ MicrovmInitialization ();\r
+ PcdStatus = PcdSet16S (\r
+ PcdOvmfHostBridgePciDevId,\r
+ MICROVM_PSEUDO_DEVICE_ID\r
+ );\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ return;\r
+ case CLOUDHV_DEVICE_ID:\r
+ DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));\r
+ PcdStatus = PcdSet16S (\r
+ PcdOvmfHostBridgePciDevId,\r
+ CLOUDHV_DEVICE_ID\r
+ );\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ return;\r
default:\r
- DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
- __FUNCTION__, mHostBridgeDevId));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ __FUNCTION__,\r
+ mHostBridgeDevId\r
+ ));\r
ASSERT (FALSE);\r
return;\r
}\r
+\r
PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
//\r
- // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
- // has been configured (e.g., by Xen) and skip the setup here.\r
- // This matches the logic in AcpiTimerLibConstructor ().\r
+ // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has\r
+ // been configured and skip the setup here. This matches the logic in\r
+ // AcpiTimerLibConstructor ().\r
//\r
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
//\r
}\r
}\r
\r
-\r
VOID\r
BootModeInitialization (\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (CmosRead8 (0xF) == 0xFE) {\r
mBootMode = BOOT_ON_S3_RESUME;\r
}\r
+\r
CmosWrite8 (0xF, 0x00);\r
\r
Status = PeiServicesSetBootMode (mBootMode);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
-\r
VOID\r
ReserveEmuVariableNvStore (\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS VariableStore;\r
- RETURN_STATUS PcdStatus;\r
+ EFI_PHYSICAL_ADDRESS VariableStore;\r
+ RETURN_STATUS PcdStatus;\r
\r
//\r
// Allocate storage for NV variables early on so it will be\r
//\r
VariableStore =\r
(EFI_PHYSICAL_ADDRESS)(UINTN)\r
- AllocateRuntimePages (\r
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
- );\r
- DEBUG ((DEBUG_INFO,\r
- "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
- VariableStore,\r
- (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
- ));\r
+ AllocateRuntimePages (\r
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
+ );\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
+ VariableStore,\r
+ (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
+ ));\r
PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-\r
VOID\r
DebugDumpCmos (\r
VOID\r
)\r
{\r
- UINT32 Loop;\r
+ UINT32 Loop;\r
\r
DEBUG ((DEBUG_INFO, "CMOS:\n"));\r
\r
if ((Loop % 0x10) == 0) {\r
DEBUG ((DEBUG_INFO, "%02x:", Loop));\r
}\r
+\r
DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));\r
if ((Loop % 0x10) == 0xf) {\r
DEBUG ((DEBUG_INFO, "\n"));\r
}\r
}\r
\r
-\r
VOID\r
S3Verification (\r
VOID\r
)\r
{\r
-#if defined (MDE_CPU_X64)\r
+ #if defined (MDE_CPU_X64)\r
if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
- DEBUG ((DEBUG_ERROR,\r
- "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
- DEBUG ((DEBUG_ERROR,\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",\r
+ __FUNCTION__\r
+ ));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
"%a: Please disable S3 on the QEMU command line (see the README),\n",\r
- __FUNCTION__));\r
- DEBUG ((DEBUG_ERROR,\r
- "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
+ __FUNCTION__\r
+ ));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",\r
+ __FUNCTION__\r
+ ));\r
ASSERT (FALSE);\r
CpuDeadLoop ();\r
}\r
-#endif\r
-}\r
\r
+ #endif\r
+}\r
\r
VOID\r
Q35BoardVerification (\r
CpuDeadLoop ();\r
}\r
\r
-\r
/**\r
Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
them to UefiCpuPkg modules. Set the mMaxCpuCount variable.\r
VOID\r
)\r
{\r
- UINT16 BootCpuCount;\r
- RETURN_STATUS PcdStatus;\r
+ UINT16 BootCpuCount;\r
+ RETURN_STATUS PcdStatus;\r
\r
//\r
// Try to fetch the boot CPU count.\r
//\r
// Now try to fetch the possible CPU count.\r
//\r
- UINTN CpuHpBase;\r
- UINT32 CmdData2;\r
+ UINTN CpuHpBase;\r
+ UINT32 CmdData2;\r
\r
CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r
ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);\r
// QEMU doesn't support the modern CPU hotplug interface. Assume that the\r
// possible CPU count equals the boot CPU count (precluding hotplug).\r
//\r
- DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: modern CPU hotplug interface unavailable\n",\r
+ __FUNCTION__\r
+ ));\r
mMaxCpuCount = BootCpuCount;\r
} else {\r
//\r
// Grab the possible CPU count from the modern CPU hotplug interface.\r
//\r
- UINT32 Present, Possible, Selected;\r
+ UINT32 Present, Possible, Selected;\r
\r
- Present = 0;\r
+ Present = 0;\r
Possible = 0;\r
\r
//\r
IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r
\r
do {\r
- UINT8 CpuStatus;\r
+ UINT8 CpuStatus;\r
\r
//\r
// Read the status of the currently selected CPU. This will help with a\r
if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {\r
++Present;\r
}\r
+\r
//\r
// Attempt to select the next CPU.\r
//\r
// return the same boot CPU count.\r
//\r
if (BootCpuCount != Present) {\r
- DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "\r
- "Present=%u\n", __FUNCTION__, BootCpuCount, Present));\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: QEMU v2.7 reset bug: BootCpuCount=%d "\r
+ "Present=%u\n",\r
+ __FUNCTION__,\r
+ BootCpuCount,\r
+ Present\r
+ ));\r
//\r
// The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus\r
// platform reset (including S3), was corrected in QEMU commit\r
}\r
}\r
\r
- DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,\r
- BootCpuCount, mMaxCpuCount));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: BootCpuCount=%d mMaxCpuCount=%u\n",\r
+ __FUNCTION__,\r
+ BootCpuCount,\r
+ mMaxCpuCount\r
+ ));\r
ASSERT (BootCpuCount <= mMaxCpuCount);\r
\r
PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-\r
/**\r
Perform Platform PEI initialization.\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
\r
- XenDetect ();\r
-\r
if (QemuFwCfgS3Enabled ()) {\r
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r
mS3Supported = TRUE;\r
- Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
InitializeRamRegions ();\r
\r
- if (mXen) {\r
- DEBUG ((DEBUG_INFO, "Xen was detected\n"));\r
- InitializeXen ();\r
- }\r
-\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
ReserveEmuVariableNvStore ();\r
}\r
+\r
PeiFvInitialization ();\r
MemTypeInfoInitialization ();\r
MemMapInitialization ();\r
projects / mirror_edk2.git / blobdiff