The exception table information in X64 PE/COFF images is being stripped by default...

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 6ea9ae31990f083fa99c5201ebcbb821a33e077a..e7486b7b7303e54c9f209010b92a45d8e76f0633 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -33,6 +33,7 @@
 #include <Library/ResourcePublicationLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/Pci22.h>\r
 \r
 #include "Platform.h"\r
 #include "Cmos.h"\r
@@ -196,14 +197,15 @@ MemMapInitialization (
   //\r
   // address       purpose   size\r
   // ------------  --------  -------------------------\r
-  // max(top, 2g)  PCI MMIO  0xFEC00000 - max(top, 2g)\r
+  // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
+  // 0xFC000000    gap                           44 MB\r
   // 0xFEC00000    IO-APIC                        4 KB\r
   // 0xFEC01000    gap                         1020 KB\r
   // 0xFED00000    HPET                           1 KB\r
   // 0xFED00400    gap                         1023 KB\r
   // 0xFEE00000    LAPIC                          1 MB\r
   //\r
-  AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFEC00000);\r
+  AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
   AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
   AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
   AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
@@ -212,7 +214,7 @@ MemMapInitialization (
 \r
 VOID\r
 MiscInitialization (\r
-  BOOLEAN Xen\r
+  VOID\r
   )\r
 {\r
   //\r
@@ -225,11 +227,34 @@ MiscInitialization (
   //\r
   BuildCpuHob (36, 16);\r
 \r
-  if (!Xen) {\r
+  //\r
+  // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
+  // example by Xen) and skip the setup here. This matches the logic in\r
+  // AcpiTimerLibConstructor ().\r
+  //\r
+  if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
+    //\r
+    // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+    // 1. set PMBA\r
+    //\r
+    PciAndThenOr32 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
+      (UINT32) ~0xFFC0,\r
+      PcdGet16 (PcdAcpiPmBaseAddress)\r
+      );\r
+\r
+    //\r
+    // 2. set PCICMD/IOSE\r
+    //\r
+    PciOr8 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
+      EFI_PCI_COMMAND_IO_SPACE\r
+      );\r
+\r
     //\r
-    // Set the PM I/O base address to 0x400\r
+    // 3. set PMREGMISC/PMIOSE\r
     //\r
-    PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
+    PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
   }\r
 }\r
 \r
@@ -311,9 +336,7 @@ InitializePlatform (
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r
-  EFI_STATUS            Status;\r
   EFI_PHYSICAL_ADDRESS  TopOfMemory;\r
-  BOOLEAN               Xen;\r
 \r
   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
 \r
@@ -321,8 +344,7 @@ InitializePlatform (
 \r
   TopOfMemory = MemDetect ();\r
 \r
-  Status = InitializeXen ();\r
-  Xen = EFI_ERROR (Status) ? FALSE : TRUE;\r
+  InitializeXen ();\r
 \r
   ReserveEmuVariableNvStore ();\r
 \r
@@ -330,7 +352,7 @@ InitializePlatform (
 \r
   MemMapInitialization (TopOfMemory);\r
 \r
-  MiscInitialization (Xen);\r
+  MiscInitialization ();\r
 \r
   BootModeInitialization ();\r
 \r