When SOURCE_DEBUG_ENABLE is set, a TimerLib is linked into the SEC Phase to support...

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index fe25486fa4afa668ea3483f237d4a4786dc6274b..e7486b7b7303e54c9f209010b92a45d8e76f0633 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -1,7 +1,9 @@
 /**@file\r
   Platform PEI driver\r
 \r
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -27,8 +29,11 @@
 #include <Library/PcdLib.h>\r
 #include <Library/PciLib.h>\r
 #include <Library/PeimEntryPoint.h>\r
+#include <Library/PeiServicesLib.h>\r
 #include <Library/ResourcePublicationLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/Pci22.h>\r
 \r
 #include "Platform.h"\r
 #include "Cmos.h"\r
@@ -45,6 +50,15 @@ EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
 };\r
 \r
 \r
+EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+    &gEfiPeiMasterBootModePpiGuid,\r
+    NULL\r
+  }\r
+};\r
+\r
+\r
 VOID\r
 AddIoMemoryBaseSizeHob (\r
   EFI_PHYSICAL_ADDRESS        MemoryBase,\r
@@ -62,6 +76,22 @@ AddIoMemoryBaseSizeHob (
     );\r
 }\r
 \r
+VOID\r
+AddReservedMemoryBaseSizeHob (\r
+  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
+  UINT64                      MemorySize\r
+  )\r
+{\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_RESERVED,\r
+      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+    MemoryBase,\r
+    MemorySize\r
+    );\r
+}\r
 \r
 VOID\r
 AddIoMemoryRangeHob (\r
@@ -153,40 +183,38 @@ MemMapInitialization (
   //\r
   BuildResourceDescriptorHob (\r
     EFI_RESOURCE_IO,\r
-      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
-      EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
-    0x1000,\r
-    0xF000\r
+    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+    0xC000,\r
+    0x4000\r
     );\r
 \r
   //\r
-  // Add PCI MMIO space available to PCI resource allocations\r
-  //\r
-  if (TopOfMemory < BASE_2GB) {\r
-    AddIoMemoryBaseSizeHob (BASE_2GB, 0xFEC00000 - BASE_2GB);\r
-  } else {\r
-    AddIoMemoryBaseSizeHob (TopOfMemory, 0xFEC00000 - TopOfMemory);\r
-  }\r
-\r
-  //\r
-  // Local APIC range\r
-  //\r
-  AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
-\r
-  //\r
-  // I/O APIC range\r
+  // Video memory + Legacy BIOS region\r
   //\r
-  AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
+  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
 \r
   //\r
-  // Video memory + Legacy BIOS region\r
+  // address       purpose   size\r
+  // ------------  --------  -------------------------\r
+  // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
+  // 0xFC000000    gap                           44 MB\r
+  // 0xFEC00000    IO-APIC                        4 KB\r
+  // 0xFEC01000    gap                         1020 KB\r
+  // 0xFED00000    HPET                           1 KB\r
+  // 0xFED00400    gap                         1023 KB\r
+  // 0xFEE00000    LAPIC                          1 MB\r
   //\r
-  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+  AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
+  AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+  AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+  AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
 }\r
 \r
 \r
 VOID\r
 MiscInitialization (\r
+  VOID\r
   )\r
 {\r
   //\r
@@ -200,9 +228,48 @@ MiscInitialization (
   BuildCpuHob (36, 16);\r
 \r
   //\r
-  // Set the PM I/O base address to 0x400\r
+  // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
+  // example by Xen) and skip the setup here. This matches the logic in\r
+  // AcpiTimerLibConstructor ().\r
   //\r
-  PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
+  if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
+    //\r
+    // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+    // 1. set PMBA\r
+    //\r
+    PciAndThenOr32 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
+      (UINT32) ~0xFFC0,\r
+      PcdGet16 (PcdAcpiPmBaseAddress)\r
+      );\r
+\r
+    //\r
+    // 2. set PCICMD/IOSE\r
+    //\r
+    PciOr8 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
+      EFI_PCI_COMMAND_IO_SPACE\r
+      );\r
+\r
+    //\r
+    // 3. set PMREGMISC/PMIOSE\r
+    //\r
+    PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
+  }\r
+}\r
+\r
+\r
+VOID\r
+BootModeInitialization (\r
+  )\r
+{\r
+  EFI_STATUS Status;\r
+\r
+  Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = PeiServicesInstallPpi (mPpiBootMode);\r
+  ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
 \r
@@ -277,6 +344,8 @@ InitializePlatform (
 \r
   TopOfMemory = MemDetect ();\r
 \r
+  InitializeXen ();\r
+\r
   ReserveEmuVariableNvStore ();\r
 \r
   PeiFvInitialization ();\r
@@ -285,5 +354,7 @@ InitializePlatform (
 \r
   MiscInitialization ();\r
 \r
+  BootModeInitialization ();\r
+\r
   return EFI_SUCCESS;\r
 }\r