#include <IndustryStandard/Pci22.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/QemuCpuHotplug.h>\r
+#include <Library/MemEncryptSevLib.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
-#include "Cmos.h"\r
+\r
+EFI_HOB_PLATFORM_INFO mPlatformInfoHob = { 0 };\r
\r
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
{\r
}\r
};\r
\r
-UINT16 mHostBridgeDevId;\r
-\r
-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
-\r
-BOOLEAN mS3Supported = FALSE;\r
-\r
-UINT32 mMaxCpuCount;\r
-\r
-VOID\r
-AddIoMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_MEMORY_MAPPED_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-VOID\r
-AddReservedMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize,\r
- BOOLEAN Cacheable\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_MEMORY_RESERVED,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- (Cacheable ?\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
- 0\r
- ) |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-VOID\r
-AddIoMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
-VOID\r
-AddMemoryBaseSizeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
- )\r
-{\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- MemoryBase,\r
- MemorySize\r
- );\r
-}\r
-\r
-VOID\r
-AddMemoryRangeHob (\r
- EFI_PHYSICAL_ADDRESS MemoryBase,\r
- EFI_PHYSICAL_ADDRESS MemoryLimit\r
- )\r
-{\r
- AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
VOID\r
MemMapInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
UINT64 PciIoBase;\r
//\r
// Video memory + Legacy BIOS region\r
//\r
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+ PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
- if (mHostBridgeDevId == 0xffff /* microvm */) {\r
- AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r
- AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r
+ if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {\r
+ PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r
+ PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r
+ PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r
return;\r
}\r
\r
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+ TopOfLowRam = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
PciExBarBase = 0;\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// The MMCONFIG area is expected to fall between the top of low RAM and\r
// the base of the 32-bit PCI host aperture.\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
} else {\r
- ASSERT (TopOfLowRam <= mQemuUc32Base);\r
- PciBase = mQemuUc32Base;\r
+ ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base);\r
+ PciBase = PlatformInfoHob->Uc32Base;\r
}\r
\r
//\r
// 0xFEE00000 LAPIC 1 MB\r
//\r
PciSize = 0xFC000000 - PciBase;\r
- AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
+ PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);\r
PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+ PlatformInfoHob->PcdPciMmio32Base = PciBase;\r
+ PlatformInfoHob->PcdPciMmio32Size = PciSize;\r
+\r
+ PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
//\r
// Note: there should be an\r
//\r
- // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
+ // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
//\r
// call below, just like the one above for RCBA. However, Linux insists\r
// that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
// is most definitely not RAM; so, as an exception, cover it with\r
// uncacheable reserved memory right here.\r
//\r
- AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
+ PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
BuildMemoryAllocationHob (\r
PciExBarBase,\r
SIZE_256MB,\r
);\r
}\r
\r
- AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+ PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
\r
//\r
// On Q35, the IO Port space is available for PCI resource allocations from\r
// 0x6000 up.\r
//\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
PciIoBase = 0x6000;\r
PciIoSize = 0xA000;\r
ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
+ PlatformInfoHob->PcdPciIoBase = PciIoBase;\r
+ PlatformInfoHob->PcdPciIoSize = PciIoSize;\r
}\r
\r
#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
*FdtHobData = (UINTN)NewBase;\r
}\r
\r
+VOID\r
+MiscInitializationForMicrovm (\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
+ )\r
+{\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ ASSERT (PlatformInfoHob->HostBridgeDevId == 0xffff);\r
+\r
+ DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r
+ //\r
+ // Disable A20 Mask\r
+ //\r
+ IoOr8 (0x92, BIT1);\r
+\r
+ //\r
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+ // S3 resume as well, so we build it unconditionally.)\r
+ //\r
+ BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);\r
+\r
+ MicrovmInitialization ();\r
+ PcdStatus = PcdSet16S (\r
+ PcdOvmfHostBridgePciDevId,\r
+ MICROVM_PSEUDO_DEVICE_ID\r
+ );\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+}\r
+\r
VOID\r
MiscInitialization (\r
- VOID\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
UINTN PmCmd;\r
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
// S3 resume as well, so we build it unconditionally.)\r
//\r
- BuildCpuHob (mPhysMemAddressWidth, 16);\r
+ BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);\r
\r
//\r
// Determine platform type and save Host Bridge DID to PCD\r
//\r
- switch (mHostBridgeDevId) {\r
+ switch (PlatformInfoHob->HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
- case 0xffff: /* microvm */\r
- DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r
- MicrovmInitialization ();\r
- PcdStatus = PcdSet16S (\r
- PcdOvmfHostBridgePciDevId,\r
- MICROVM_PSEUDO_DEVICE_ID\r
- );\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
- return;\r
case CLOUDHV_DEVICE_ID:\r
- DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));\r
- PcdStatus = PcdSet16S (\r
- PcdOvmfHostBridgePciDevId,\r
- CLOUDHV_DEVICE_ID\r
- );\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
- return;\r
+ break;\r
default:\r
DEBUG ((\r
DEBUG_ERROR,\r
"%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
__FUNCTION__,\r
- mHostBridgeDevId\r
+ PlatformInfoHob->HostBridgeDevId\r
));\r
ASSERT (FALSE);\r
return;\r
}\r
\r
- PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
+ if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {\r
+ DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));\r
+ return;\r
+ }\r
+\r
//\r
// If the appropriate IOspace enable bit is set, assume the ACPI PMBA has\r
// been configured and skip the setup here. This matches the logic in\r
PciOr8 (AcpiCtlReg, AcpiEnBit);\r
}\r
\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// Set Root Complex Register Block BAR\r
//\r
\r
VOID\r
BootModeInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
EFI_STATUS Status;\r
\r
- if (CmosRead8 (0xF) == 0xFE) {\r
- mBootMode = BOOT_ON_S3_RESUME;\r
+ if (PlatformCmosRead8 (0xF) == 0xFE) {\r
+ PlatformInfoHob->BootMode = BOOT_ON_S3_RESUME;\r
}\r
\r
- CmosWrite8 (0xF, 0x00);\r
+ PlatformCmosWrite8 (0xF, 0x00);\r
\r
- Status = PeiServicesSetBootMode (mBootMode);\r
+ Status = PeiServicesSetBootMode (PlatformInfoHob->BootMode);\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = PeiServicesInstallPpi (mPpiBootMode);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-VOID\r
-DebugDumpCmos (\r
- VOID\r
- )\r
-{\r
- UINT32 Loop;\r
-\r
- DEBUG ((DEBUG_INFO, "CMOS:\n"));\r
-\r
- for (Loop = 0; Loop < 0x80; Loop++) {\r
- if ((Loop % 0x10) == 0) {\r
- DEBUG ((DEBUG_INFO, "%02x:", Loop));\r
- }\r
-\r
- DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));\r
- if ((Loop % 0x10) == 0xf) {\r
- DEBUG ((DEBUG_INFO, "\n"));\r
- }\r
- }\r
-}\r
-\r
VOID\r
S3Verification (\r
VOID\r
)\r
{\r
#if defined (MDE_CPU_X64)\r
- if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) {\r
DEBUG ((\r
DEBUG_ERROR,\r
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",\r
VOID\r
)\r
{\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ if (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
return;\r
}\r
\r
"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
"only DID=0x%04x (Q35) is supported\n",\r
__FUNCTION__,\r
- mHostBridgeDevId,\r
+ mPlatformInfoHob.HostBridgeDevId,\r
INTEL_Q35_MCH_DEVICE_ID\r
));\r
ASSERT (FALSE);\r
\r
/**\r
Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
- them to UefiCpuPkg modules. Set the mMaxCpuCount variable.\r
+ them to UefiCpuPkg modules. Set the MaxCpuCount field in PlatformInfoHob.\r
**/\r
VOID\r
-MaxCpuCountInitialization (\r
- VOID\r
+PlatformMaxCpuCountInitialization (\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- UINT16 BootCpuCount;\r
- RETURN_STATUS PcdStatus;\r
+ UINT16 BootCpuCount;\r
+ UINT32 MaxCpuCount;\r
\r
//\r
// Try to fetch the boot CPU count.\r
// first).\r
//\r
DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));\r
- mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+ MaxCpuCount = PlatformInfoHob->DefaultMaxCpuNumber;\r
} else {\r
//\r
// We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to\r
UINTN CpuHpBase;\r
UINT32 CmdData2;\r
\r
- CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r
+ CpuHpBase = ((PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r
ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);\r
\r
//\r
"%a: modern CPU hotplug interface unavailable\n",\r
__FUNCTION__\r
));\r
- mMaxCpuCount = BootCpuCount;\r
+ MaxCpuCount = BootCpuCount;\r
} else {\r
//\r
// Grab the possible CPU count from the modern CPU hotplug interface.\r
BootCpuCount = (UINT16)Present;\r
}\r
\r
- mMaxCpuCount = Possible;\r
+ MaxCpuCount = Possible;\r
}\r
}\r
\r
DEBUG ((\r
DEBUG_INFO,\r
- "%a: BootCpuCount=%d mMaxCpuCount=%u\n",\r
+ "%a: BootCpuCount=%d MaxCpuCount=%u\n",\r
__FUNCTION__,\r
BootCpuCount,\r
- mMaxCpuCount\r
+ MaxCpuCount\r
));\r
- ASSERT (BootCpuCount <= mMaxCpuCount);\r
+ ASSERT (BootCpuCount <= MaxCpuCount);\r
+\r
+ PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber = MaxCpuCount;\r
+ PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;\r
+}\r
\r
- PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);\r
+/**\r
+ Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
+ them to UefiCpuPkg modules. Set the MaxCpuCount field in PlatformInfoHob.\r
+**/\r
+VOID\r
+MaxCpuCountInitialization (\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
+ )\r
+{\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ PlatformMaxCpuCountInitialization (PlatformInfoHob);\r
+\r
+ PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, PlatformInfoHob->PcdCpuBootLogicalProcessorNumber);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);\r
+ PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
\r
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
\r
- DebugDumpCmos ();\r
+ mPlatformInfoHob.SmmSmramRequire = FeaturePcdGet (PcdSmmSmramRequire);\r
+ mPlatformInfoHob.SevEsIsEnabled = MemEncryptSevEsIsEnabled ();\r
+ mPlatformInfoHob.PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);\r
+ mPlatformInfoHob.DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+\r
+ PlatformDebugDumpCmos ();\r
\r
if (QemuFwCfgS3Enabled ()) {\r
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r
- mS3Supported = TRUE;\r
- Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
+ mPlatformInfoHob.S3Supported = TRUE;\r
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
S3Verification ();\r
- BootModeInitialization ();\r
- AddressWidthInitialization ();\r
+ BootModeInitialization (&mPlatformInfoHob);\r
+ AddressWidthInitialization (&mPlatformInfoHob);\r
\r
//\r
// Query Host Bridge DID\r
//\r
- mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+ mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
- MaxCpuCountInitialization ();\r
+ MaxCpuCountInitialization (&mPlatformInfoHob);\r
\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ if (mPlatformInfoHob.SmmSmramRequire) {\r
Q35BoardVerification ();\r
Q35TsegMbytesInitialization ();\r
Q35SmramAtDefaultSmbaseInitialization ();\r
\r
PublishPeiMemory ();\r
\r
- QemuUc32BaseInitialization ();\r
+ PlatformQemuUc32BaseInitialization (&mPlatformInfoHob);\r
\r
- InitializeRamRegions ();\r
+ InitializeRamRegions (&mPlatformInfoHob);\r
\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
- if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ if (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME) {\r
+ if (!mPlatformInfoHob.SmmSmramRequire) {\r
ReserveEmuVariableNvStore ();\r
}\r
\r
PeiFvInitialization ();\r
MemTypeInfoInitialization ();\r
- MemMapInitialization ();\r
+ MemMapInitialization (&mPlatformInfoHob);\r
NoexecDxeInitialization ();\r
}\r
\r
InstallClearCacheCallback ();\r
AmdSevInitialize ();\r
- MiscInitialization ();\r
+ if (mPlatformInfoHob.HostBridgeDevId == 0xffff) {\r
+ MiscInitializationForMicrovm (&mPlatformInfoHob);\r
+ } else {\r
+ MiscInitialization (&mPlatformInfoHob);\r
+ }\r
+\r
InstallFeatureControlCallback ();\r
\r
return EFI_SUCCESS;\r
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