Bug fix in PatchFv.py for GCC build in IntelFspPkg.

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 0e41d305c7dcf9c6e6e6e8d04edcfabf1ee57b77..fc98fc35e0781a88385ad015b7fcf3cd9f539319 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -32,9 +32,11 @@
 #include <Library/PeiServicesLib.h>\r
 #include <Library/QemuFwCfgLib.h>\r
 #include <Library/ResourcePublicationLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
 #include <IndustryStandard/Pci22.h>\r
+#include <IndustryStandard/SmBios.h>\r
 #include <OvmfPlatforms.h>\r
 \r
 #include "Platform.h"\r
@@ -214,13 +216,18 @@ MemMapInitialization (
     // 0xFEC00000    IO-APIC                        4 KB\r
     // 0xFEC01000    gap                         1020 KB\r
     // 0xFED00000    HPET                           1 KB\r
-    // 0xFED00400    gap                         1023 KB\r
+    // 0xFED00400    gap                          111 KB\r
+    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
+    // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
     AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
                          BASE_2GB : TopOfLowRam, 0xFC000000);\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+    }\r
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
   }\r
 }\r
@@ -242,9 +249,11 @@ MiscInitialization (
   IoOr8 (0x92, BIT1);\r
 \r
   //\r
-  // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+  // S3 resume as well, so we build it unconditionally.)\r
   //\r
-  BuildCpuHob (36, 16);\r
+  BuildCpuHob (mPhysMemAddressWidth, 16);\r
 \r
   //\r
   // Determine platform type and save Host Bridge DID to PCD\r
@@ -292,6 +301,16 @@ MiscInitialization (
     //\r
     PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
+\r
+  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+    //\r
+    // Set Root Complex Register Block BAR\r
+    //\r
+    PciWrite32 (\r
+      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
+      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
+      );\r
+  }\r
 }\r
 \r
 \r
@@ -362,6 +381,41 @@ DebugDumpCmos (
 }\r
 \r
 \r
+/**\r
+  Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
+**/\r
+STATIC\r
+VOID\r
+SmbiosVersionInitialization (\r
+  VOID\r
+  )\r
+{\r
+  FIRMWARE_CONFIG_ITEM     Anchor;\r
+  UINTN                    AnchorSize;\r
+  SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
+  UINT16                   SmbiosVersion;\r
+\r
+  if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
+                      &AnchorSize)) ||\r
+      AnchorSize != sizeof QemuAnchor) {\r
+    return;\r
+  }\r
+\r
+  QemuFwCfgSelectItem (Anchor);\r
+  QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
+  if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||\r
+      CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
+    return;\r
+  }\r
+\r
+  SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |\r
+                           QemuAnchor.MinorVersion);\r
+  DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
+    SmbiosVersion));\r
+  PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
+}\r
+\r
+\r
 /**\r
   Perform Platform PEI initialization.\r
 \r
@@ -390,6 +444,7 @@ InitializePlatform (
   }\r
 \r
   BootModeInitialization ();\r
+  AddressWidthInitialization ();\r
 \r
   PublishPeiMemory ();\r
 \r
@@ -411,6 +466,8 @@ InitializePlatform (
     PeiFvInitialization ();\r
 \r
     MemMapInitialization ();\r
+\r
+    SmbiosVersionInitialization ();\r
   }\r
 \r
   MiscInitialization ();\r