/**@file\r
Platform PEI driver\r
\r
- Copyright (c) 2006 - 2009, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
#include <Guid/MemoryTypeInformation.h>\r
\r
#include "Platform.h"\r
+#include "Cmos.h"\r
\r
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
{ EfiACPIMemoryNVS, 0x004 },\r
- { EfiACPIReclaimMemory, 0x01C },\r
- { EfiRuntimeServicesData, 0x050 },\r
- { EfiRuntimeServicesCode, 0x020 },\r
- { EfiBootServicesCode, 0x0F0 },\r
- { EfiBootServicesData, 0xA00 },\r
+ { EfiACPIReclaimMemory, 0x008 },\r
+ { EfiReservedMemoryType, 0x004 },\r
+ { EfiRuntimeServicesData, 0x024 },\r
+ { EfiRuntimeServicesCode, 0x030 },\r
+ { EfiBootServicesCode, 0x180 },\r
+ { EfiBootServicesData, 0xF00 },\r
{ EfiMaxMemoryType, 0x000 }\r
};\r
\r
UINT64 MemorySize\r
)\r
{\r
- STATIC EFI_RESOURCE_ATTRIBUTE_TYPE Attributes =\r
- (\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_MAPPED_IO,\r
EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED\r
- );\r
-\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_MEMORY_MAPPED_IO,\r
- Attributes,\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
MemoryBase,\r
MemorySize\r
);\r
UINT64 MemorySize\r
)\r
{\r
- STATIC EFI_RESOURCE_ATTRIBUTE_TYPE Attributes =\r
- (\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+ MemoryBase,\r
+ MemorySize\r
);\r
+}\r
+\r
+\r
+VOID\r
+AddMemoryRangeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ )\r
+{\r
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
+}\r
\r
+\r
+VOID\r
+AddUntestedMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ )\r
+{\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_SYSTEM_MEMORY,\r
- Attributes,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
MemoryBase,\r
MemorySize\r
);\r
\r
\r
VOID\r
-AddMemoryRangeHob (\r
+AddUntestedMemoryRangeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
EFI_PHYSICAL_ADDRESS MemoryLimit\r
)\r
{\r
- AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
+ AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
MemMapInitialization (\r
+ EFI_PHYSICAL_ADDRESS TopOfMemory\r
)\r
{\r
//\r
sizeof(mDefaultMemoryTypeInformation)\r
);\r
\r
+ //\r
+ // Add PCI IO Port space available for PCI resource allocations.\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_IO,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
+ 0x1000,\r
+ 0xF000\r
+ );\r
+\r
+ //\r
+ // Add PCI MMIO space available to PCI resource allocations\r
+ //\r
+ if (TopOfMemory < BASE_2GB) {\r
+ AddIoMemoryBaseSizeHob (BASE_2GB, 0xFEC00000 - BASE_2GB);\r
+ } else {\r
+ AddIoMemoryBaseSizeHob (TopOfMemory, 0xFEC00000 - TopOfMemory);\r
+ }\r
+\r
//\r
// Local APIC range\r
//\r
- AddIoMemoryBaseSizeHob (0xFEC80000, 0x80000);\r
+ AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
\r
//\r
// I/O APIC range\r
//\r
- AddIoMemoryBaseSizeHob (0xFEC00000, 0x80000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
\r
//\r
// Video memory + Legacy BIOS region\r
//\r
- AddIoMemoryRangeHob (0x0A0000, 0x100000);\r
+ AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
}\r
\r
\r
//\r
// Disable A20 Mask\r
//\r
- IoWrite8 (0x92, (UINT8) (IoRead8 (0x92) | 0x02));\r
+ IoOr8 (0x92, BIT1);\r
\r
//\r
// Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
//\r
BuildCpuHob (36, 16);\r
+\r
+ //\r
+ // Set the PM I/O base address to 0x400\r
+ //\r
+ PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
}\r
\r
\r
VariableStore =\r
(EFI_PHYSICAL_ADDRESS)(UINTN)\r
AllocateRuntimePool (\r
- 2 * FixedPcdGet32(PcdFlashNvStorageFtwSpareSize)\r
+ 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
);\r
DEBUG ((EFI_D_INFO,\r
"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
VariableStore,\r
- (2 * FixedPcdGet32(PcdFlashNvStorageFtwSpareSize)) / 1024\r
+ (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
));\r
PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
}\r
\r
\r
+VOID\r
+DebugDumpCmos (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Loop;\r
+\r
+ DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
+\r
+ for (Loop = 0; Loop < 0x80; Loop++) {\r
+ if ((Loop % 0x10) == 0) {\r
+ DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
+ }\r
+ DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
+ if ((Loop % 0x10) == 0xf) {\r
+ DEBUG ((EFI_D_INFO, "\n"));\r
+ }\r
+ }\r
+}\r
+\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
+ EFI_PHYSICAL_ADDRESS TopOfMemory;\r
+\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
- MemDetect ();\r
+ DebugDumpCmos ();\r
+\r
+ TopOfMemory = MemDetect ();\r
\r
ReserveEmuVariableNvStore ();\r
\r
PeiFvInitialization ();\r
\r
- MemMapInitialization ();\r
+ MemMapInitialization (TopOfMemory);\r
\r
MiscInitialization ();\r
\r
return EFI_SUCCESS;\r
}\r
-\r
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