Copyright (C) 2014, Red Hat, Inc.\r
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <IndustryStandard/LegacyVgaBios.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PrintLib.h>\r
+#include <OvmfPlatforms.h>\r
\r
#include "Qemu.h"\r
#include "VbeShim.h"\r
UINTN Segment0Pages;\r
IVT_ENTRY *Int0x10;\r
EFI_STATUS Segment0AllocationStatus;\r
+ UINT16 HostBridgeDevId;\r
UINTN Pam1Address;\r
UINT8 Pam1;\r
UINTN SegmentCPages;\r
UINTN Printed;\r
VBE_MODE_INFO *VbeModeInfo;\r
\r
+ if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT0|BIT7)) == BIT0) {\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: page 0 protected, not installing VBE shim\n",\r
+ __FUNCTION__\r
+ ));\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: page 0 protection prevents Windows 7 from booting anyway\n",\r
+ __FUNCTION__\r
+ ));\r
+ return;\r
+ }\r
+\r
Segment0 = 0x00000;\r
SegmentC = 0xC0000;\r
SegmentF = 0xF0000;\r
// The allocation request may fail, eg. if LegacyBiosDxe has already run.\r
//\r
Segment0Pages = 1;\r
- Int0x10 = (IVT_ENTRY *)(UINTN)Segment0 + 0x10;\r
+ Int0x10 = (IVT_ENTRY *)(UINTN)(Segment0 + 0x10 * sizeof (IVT_ENTRY));\r
Segment0AllocationStatus = gBS->AllocatePages (\r
AllocateAddress,\r
EfiBootServicesCode,\r
//\r
// Put the shim in place first.\r
//\r
- Pam1Address = PCI_LIB_ADDRESS (0, 0, 0, 0x5A);\r
+ // Start by determining the address of the PAM1 register.\r
+ //\r
+ HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
+ switch (HostBridgeDevId) {\r
+ case INTEL_82441_DEVICE_ID:\r
+ Pam1Address = PMC_REGISTER_PIIX4 (PIIX4_PAM1);\r
+ break;\r
+ case INTEL_Q35_MCH_DEVICE_ID:\r
+ Pam1Address = DRAMC_REGISTER_Q35 (MCH_PAM1);\r
+ break;\r
+ default:\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: unknown host bridge device ID: 0x%04x\n",\r
+ __FUNCTION__,\r
+ HostBridgeDevId\r
+ ));\r
+ ASSERT (FALSE);\r
+\r
+ if (!EFI_ERROR (Segment0AllocationStatus)) {\r
+ gBS->FreePages (Segment0, Segment0Pages);\r
+ }\r
+ return;\r
+ }\r
//\r
// low nibble covers 0xC0000 to 0xC3FFF\r
// high nibble covers 0xC4000 to 0xC7FFF\r