; This file includes all other code files to assemble the reset vector code\r
;\r
; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
;------------------------------------------------------------------------------\r
%include "Ia32/SearchForBfvBase.asm"\r
%include "Ia32/SearchForSecEntry.asm"\r
\r
+%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase))\r
+\r
%ifdef ARCH_X64\r
#include <AutoGen.h>\r
\r
%endif\r
\r
%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))\r
-%include "Ia32/Flat32ToFlat64.asm"\r
\r
%define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))\r
%define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))\r
%define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))\r
%define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
+ %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)\r
+ %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)\r
%define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))\r
+%include "Ia32/Flat32ToFlat64.asm"\r
+%include "Ia32/AmdSev.asm"\r
%include "Ia32/PageTables64.asm"\r
%endif\r
\r
\r
%include "Main.asm"\r
\r
+ %define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase)\r
+ %define SEV_LAUNCH_SECRET_BASE FixedPcdGet32 (PcdSevLaunchSecretBase)\r
+ %define SEV_LAUNCH_SECRET_SIZE FixedPcdGet32 (PcdSevLaunchSecretSize)\r
+ %define SEV_FW_HASH_BLOCK_BASE FixedPcdGet32 (PcdQemuHashTableBase)\r
+ %define SEV_FW_HASH_BLOCK_SIZE FixedPcdGet32 (PcdQemuHashTableSize)\r
%include "Ia16/ResetVectorVtf0.asm"\r
\r