OvmfPkg: replace old EFI_D_ debug levels with new DEBUG_ ones

[mirror_edk2.git] / OvmfPkg / SmmAccess / SmmAccessPei.c

diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccessPei.c
index 76790e330f65154ed654f442eae5ff88ba7da801..ec4e9a2761959662eaebf46d5df7a3bc95806c70 100644 (file)
--- a/OvmfPkg/SmmAccess/SmmAccessPei.c
+++ b/OvmfPkg/SmmAccess/SmmAccessPei.c
@@ -13,13 +13,7 @@
   Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
   Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
 \r
-  This program and the accompanying materials are licensed and made available\r
-  under the terms and conditions of the BSD License which accompanies this\r
-  distribution. The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
-  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -264,7 +258,7 @@ SmmAccessPeiEntryPoint (
   //\r
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
-    DEBUG ((EFI_D_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r
+    DEBUG ((DEBUG_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r
       "DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,\r
       INTEL_Q35_MCH_DEVICE_ID));\r
     goto WrongConfig;\r
@@ -280,7 +274,7 @@ SmmAccessPeiEntryPoint (
   EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
   RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;\r
   if ((EsmramcVal & RegMask8) != RegMask8) {\r
-    DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r
+    DEBUG ((DEBUG_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r
       __FUNCTION__));\r
     goto WrongConfig;\r
   }\r
@@ -318,8 +312,9 @@ SmmAccessPeiEntryPoint (
   //\r
   // Set TSEG Memory Base.\r
   //\r
+  InitQ35TsegMbytes ();\r
   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
-    (TopOfLowRamMb - FixedPcdGet16 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT);\r
+    (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT);\r
 \r
   //\r
   // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r
@@ -327,9 +322,10 @@ SmmAccessPeiEntryPoint (
   // *restricted* to SMM.\r
   //\r
   EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;\r
-  EsmramcVal |= FixedPcdGet16 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
-                FixedPcdGet16 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
-                MCH_ESMRAMC_TSEG_1MB;\r
+  EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
+                mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
+                mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :\r
+                MCH_ESMRAMC_TSEG_EXT;\r
   EsmramcVal |= MCH_ESMRAMC_T_EN;\r
   PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);\r
 \r
@@ -355,12 +351,12 @@ SmmAccessPeiEntryPoint (
     UINTN Idx;\r
 \r
     Count = SmramMapSize / sizeof SmramMap[0];\r
-    DEBUG ((EFI_D_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r
+    DEBUG ((DEBUG_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r
       (INT32)Count));\r
-    DEBUG ((EFI_D_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r
+    DEBUG ((DEBUG_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r
       "PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));\r
     for (Idx = 0; Idx < Count; ++Idx) {\r
-      DEBUG ((EFI_D_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
+      DEBUG ((DEBUG_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
         SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,\r
         SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));\r
     }\r
@@ -376,6 +372,12 @@ SmmAccessPeiEntryPoint (
   CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState],\r
     sizeof SmramMap[DescIdxSmmS3ResumeState]);\r
 \r
+  //\r
+  // SmramAccessLock() depends on "mQ35SmramAtDefaultSmbase"; init the latter\r
+  // just before exposing the former via PEI_SMM_ACCESS_PPI.Lock().\r
+  //\r
+  InitQ35SmramAtDefaultSmbase ();\r
+\r
   //\r
   // We're done. The next step should succeed, but even if it fails, we can't\r
   // roll back the above BuildGuidHob() allocation, because PEI doesn't support\r