//\r
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
- DEBUG ((EFI_D_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r
+ DEBUG ((DEBUG_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r
"DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,\r
INTEL_Q35_MCH_DEVICE_ID));\r
goto WrongConfig;\r
EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;\r
if ((EsmramcVal & RegMask8) != RegMask8) {\r
- DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r
+ DEBUG ((DEBUG_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r
__FUNCTION__));\r
goto WrongConfig;\r
}\r
UINTN Idx;\r
\r
Count = SmramMapSize / sizeof SmramMap[0];\r
- DEBUG ((EFI_D_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r
+ DEBUG ((DEBUG_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r
(INT32)Count));\r
- DEBUG ((EFI_D_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r
+ DEBUG ((DEBUG_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r
"PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));\r
for (Idx = 0; Idx < Count; ++Idx) {\r
- DEBUG ((EFI_D_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
+ DEBUG ((DEBUG_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,\r
SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));\r
}\r