/** @file\r
- Timer Architectural Protocol module using High Precesion Event Timer (HPET)\r
+ Timer Architectural Protocol module using High Precision Event Timer (HPET)\r
\r
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
/**\r
Write a 64-bit HPET register.\r
\r
- @param Offset Specifies the ofsfert of the HPET register to write.\r
+ @param Offset Specifies the offset of the HPET register to write.\r
@param Value Specifies the value to write to the HPET register specified by Offset.\r
\r
@return The 64-bit value written to HPET register specified by Offset.\r
// If TimerPeriod is 0, then mask HPET Timer interrupts\r
//\r
\r
- if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
+ if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
//\r
// Disable HPET MSI interrupt generation\r
//\r
//\r
// Enable HPET Timer interrupt generation\r
//\r
- if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
+ if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
//\r
// Program MSI Address and MSI Data values in the selected HPET Timer\r
// Program HPET register with APIC ID of current BSP in case BSP has been switched\r
//\r
// Check to see if this HPET Timer supports MSI\r
//\r
- if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0) {\r
+ if (mTimerConfiguration.Bits.MsiInterruptCapability != 0) {\r
//\r
// Save the index of the first HPET Timer that supports MSI interrupts\r
//\r
// Show state of enabled HPET timer\r
//\r
DEBUG_CODE (\r
- if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
+ if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
DEBUG ((DEBUG_INFO, "HPET Interrupt Mode MSI\n"));\r
} else {\r
DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n"));\r