///\r
/// HPET Timer Register Offsets\r
///\r
-#define HPET_MAIN_COUNTER_OFFSET 0x0F0\r
-#define HPET_TIMER_CONFIGURATION_OFFSET 0x100\r
-#define HPET_TIMER_COMPARATOR_OFFSET 0x108\r
-#define HPET_TIMER_MSI_ROUTE_OFFSET 0x110\r
+#define HPET_MAIN_COUNTER_OFFSET 0x0F0\r
+#define HPET_TIMER_CONFIGURATION_OFFSET 0x100\r
+#define HPET_TIMER_COMPARATOR_OFFSET 0x108\r
+#define HPET_TIMER_MSI_ROUTE_OFFSET 0x110\r
\r
///\r
/// Stride between sets of HPET Timer Registers\r
///\r
-#define HPET_TIMER_STRIDE 0x20\r
+#define HPET_TIMER_STRIDE 0x20\r
\r
#pragma pack(1)\r
\r
///\r
typedef union {\r
struct {\r
- UINT32 Revision:8;\r
- UINT32 NumberOfTimers:5;\r
- UINT32 CounterSize:1;\r
- UINT32 Reserved0:1;\r
- UINT32 LegacyRoute:1;\r
- UINT32 VendorId:16;\r
- UINT32 CounterClockPeriod:32;\r
+ UINT32 Revision : 8;\r
+ UINT32 NumberOfTimers : 5;\r
+ UINT32 CounterSize : 1;\r
+ UINT32 Reserved0 : 1;\r
+ UINT32 LegacyRoute : 1;\r
+ UINT32 VendorId : 16;\r
+ UINT32 CounterClockPeriod : 32;\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} HPET_GENERAL_CAPABILITIES_ID_REGISTER;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 MainCounterEnable:1;\r
- UINT32 LegacyRouteEnable:1;\r
- UINT32 Reserved0:30;\r
- UINT32 Reserved1:32;\r
+ UINT32 MainCounterEnable : 1;\r
+ UINT32 LegacyRouteEnable : 1;\r
+ UINT32 Reserved0 : 30;\r
+ UINT32 Reserved1 : 32;\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} HPET_GENERAL_CONFIGURATION_REGISTER;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 Reserved0:1;\r
- UINT32 LevelTriggeredInterrupt:1;\r
- UINT32 InterruptEnable:1;\r
- UINT32 PeriodicInterruptEnable:1;\r
- UINT32 PeriodicInterruptCapability:1;\r
- UINT32 CounterSizeCapability:1;\r
- UINT32 ValueSetEnable:1;\r
- UINT32 Reserved1:1;\r
- UINT32 CounterSizeEnable:1;\r
- UINT32 InterruptRoute:5;\r
- UINT32 MsiInterruptEnable:1;\r
- UINT32 MsiInterruptCapability:1;\r
- UINT32 Reserved2:16;\r
- UINT32 InterruptRouteCapability;\r
+ UINT32 Reserved0 : 1;\r
+ UINT32 LevelTriggeredInterrupt : 1;\r
+ UINT32 InterruptEnable : 1;\r
+ UINT32 PeriodicInterruptEnable : 1;\r
+ UINT32 PeriodicInterruptCapability : 1;\r
+ UINT32 CounterSizeCapability : 1;\r
+ UINT32 ValueSetEnable : 1;\r
+ UINT32 Reserved1 : 1;\r
+ UINT32 CounterSizeEnable : 1;\r
+ UINT32 InterruptRoute : 5;\r
+ UINT32 MsiInterruptEnable : 1;\r
+ UINT32 MsiInterruptCapability : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 InterruptRouteCapability;\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} HPET_TIMER_CONFIGURATION_REGISTER;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 Value:32;\r
- UINT32 Address:32;\r
+ UINT32 Value : 32;\r
+ UINT32 Address : 32;\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} HPET_TIMER_MSI_ROUTE_REGISTER;\r
\r
#pragma pack()\r